如何在ZedBoard中使用AXI DMA核心

你好
最近我一直在研究如何在ZedBoard中使用AXI_DMA核心。
我正在使用s2mm通道以分散聚集模式将数据传输到DRAM。
框图如下图所示（基于Mohammadsadegh Sadri Zynq培训课程的例子。感谢他）。
我把Xilinx的例子作为软件参考，最后我可以得到这些东西工作，这意味着我得到的数据包的数量是正确的，当我查看我的DRAM区域（RX BUFFER）时，数据就像预期的那样。
数据包大小小于RX缓冲区大小，因此我可以确保每个数据包只需要一个描述符。
然而，我仍然无法使其工作的一件事是我希望每次收到一个中断，而不是每个BD RING一次中断。
我浏览了axi dma文档并明确地使用XAxiDma_BdRingSetCoalesce（RxRingPtr，1,0）来请求dma核心中断每个数据包，但是它不起作用......实际上，它似乎根本没有效果，因为
无论我放在那里的数字，每个BD Ring总是有一个中断....
如果有人可以解释我为什么会这样，那将是非常了解的。
如果有人想详细查看代码，请给我发电子邮件。
非常感谢。
玉萍



以下为原文

Hi there

Recently I’ve been studying how to use AXI_DMA core with ZedBoard. I’m using s2mm channel to transfer data to DRAM in scatter gather mode.
The block diagram is showed in the picture below (it based on the example of Mohammadsadegh Sadri Zynq training course. Thank him).

I took the Xilinx example as software reference and finally I can get this stuff somehow work, which means the number of packets I got is correct and also when I look into my DRAM area (RX BUFFER), the data there is as expected. The Packet size is smaller than the RX buffer size, so that I can make sure, that only one descriptor per packet is needed.
However one thing I still can’t make it work is that I would like to have ONE INTERRUPTION PER EACH PACKET received instead of ONE INTERRUPTION PER BD RING. I went through the axi dma document and explicitly using the XAxiDma_BdRingSetCoalesce(RxRingPtr, 1,0) to ask the dma core to interrupt every packet, but it doesn’t work….In fact, it seems it has no effect at all, because no matter what number I put there, it always one interrupts per BD Ring….

It would be very apprechiated if some one could explain me why is that.

p.s if some one would like to look into the code in detail, please just email me.

Thanks a lot.

Vicky