多个时钟问题

p，
如果您希望将时钟相位用作输出信号，则不需要使用BUFG。
你的代码不是我会用的。
相反，我会直接使用时钟相位（作为时钟）。
为同步系统正确执行此操作的另一种方法是将时钟乘以4，然后使用它来驱动计数器（或状态机）。
状态机（解码计数器）输出用作后续逻辑的时钟使能。
一个时钟，其他一切由时钟控制启用。
在FPGA器件中，简单状态机是1热状态机（4 DFF作为移位寄存器反馈自身）。
4 DFF Q成为四个启用。
Austin Lesea主要工程师Xilinx San Jose



以下为原文

p,
 
If you wish to use the clock phases as output signals, you need to NOT use the BUFG.
 
Your code is not what I would use.

Instead, I would use the clock phase directly (as a clock).
 
Another way to do this properly for a synchronous system would be to Multiply the clock by 4, mand use that to drive a counter (or a state machine).  The state machine (decoded counter) outputs are used as clock enables to subsequent logic.  One  clock, everything else controlled by clock enables.
 
In the FPGA device, the simples state machine is a 1-hot state machine (4 DFF as a shift register fed back on itself).  The 4 DFF Q become the four enables.
 
 
Austin Lesea
Principal Engineer
Xilinx San Jose

peta32387写道：
我不明白为什么“start”被称为时钟IOB组件。
它不是时钟，而是连接到其中一个GPIO引脚的输入。
当该引脚变为高电平时，计数器从零开始向上计数，并执行上面的代码。
这不是FPGA问题，而是综合问题。
“开始”是一个时钟。
你已经这样编码了。
当合成器在您拥有的模式中看到“rising_edge（any_signal_identifier）”时，它将编码寄存器，“any_signal_identifier”将连接到触发器的时钟输入。
peta32387写道：
每个信号通过BUFG路由出去。
我正在尝试在TDC中实现Nutt Interpolation。在Map过程中发生以下警告和错误：
我使用RTL原理图查看器找到了组件N11。
它是单输入/输出反相门（器件和型号= INV）。
我在示意图中跟踪了不同的时钟信号，我只是看不出它是如何认为有3个信号驱动它的。
另外，简单的问题，在这种情况下什么是“引脚”？
我只想到引脚作为开发板上的实际引脚。
什么是“非时钟引脚”？
Vivado（由于某种原因）调用普通人会想到的针脚或垫“端口”（尽管不一致，例如，某些XDC约束）。
引脚是任何模块的（VHDL）端口或Vivado中的主要端口。
在我看来，这是一个令人遗憾的命名惯例 - 非常令人困惑。
关于您的错误消息，您的CLK0，CLK90，CLK180和CLK270由BUFG驱动，但您的代码在组合逻辑（LUT）中使用它们。
因此，需要发生从全球网到通用路由的路径（通常不可取）。
我不确定您的频率是多少，但您可能需要考虑使用计数器而不是使用MMCM_ADV来生成信号。
您仍然可以将它们命名为clk180等，但只要您不将它们放在rising_edge（clk180）中，它就会使用通用路由。
您可能需要考虑VHDL培训，或VHDL和高级VHDL（精简）培训。
***我们中的许多人都是FPGA爱好者，而不是Xilinx员工。
如果您获得帮助并给予荣誉（明星），您将来可能会继续获得帮助。
如果您有解决方案，请将其标记为解决方案。***



以下为原文

 

peta32387 wrote:
 
 
I don't understand why "start" is called a clock IOB component. It's not a clock, it is a input tied to one of the GPIO pins. When that pin goes high, a counter starts counting up from zero, as well as executes the code above. 
 

This is not an FPGA issue, but a synthesis issue. 
 
"start" is a clock.  You have coded it as such.  When the synthesizer sees the "rising_edge(any_signal_identifier)" in the pattern you have, it will code a register, and the "any_signal_identifier" will get connected to the clock input of a flip flop.
 
 

peta32387 wrote:
 
 
Each signal is routed out through a BUFG. I'm trying to implement Nutt Interpolation in a TDC.The following warning and error occur during the Map process:
I found the component N11 using the RTL schematic viewer. It's a single input/output inverting gate (device and model = INV). I traced the different clock signals in the schematic, and I just don't see how it thinks there 3 signals driving it. Also, simple question, what are "pins" in this case? I've only thought of pins as the acutal, physical pins on the development board. What is a "non-clock pin"?
 
 

Vivado (for some reason) calls what normal people would think of pins or pads "ports" (though not consistently, e.g., some XDC constraints).  Pins are the (VHDL) ports of any module or primative in Vivado.  It is an unfortunate naming convention in my view--very confusing.
 
Regarding your error message, you CLK0, CLK90, CLK180 and CLK270 are being driven by BUFG's, but your code is using them in the combinatorial logic (LUTs).  Consequently, a path from a global net to general purpose routing needs to occur (generally not advisable).
 
I'm not sure what your frequencies are, but you may want to consider generating signals using a counter instead of using an MMCM_ADV.  You can still name them clk180 etc., but as long as you don't put them in a rising_edge(clk180), it will use general purpose routing.
 
You may want to consider VHDL training, or VHDL and Advanced VHDL (condensed) training.
***Many of us who help you are just FPGA enthusiasts, and not Xilinx employees.  If you receive help, and give kudos (star), you're likely to continue receiving help in the future.  If you get a solution, please mark it as a solution.***

奥斯汀，非常感谢你的回复！
你是什​​么意思，你会直接使用时钟阶段？我也尝试了下面的代码，没有合成。
对时钟信号使用四个独立的过程来尝试控制一个信号（startQuarterPeriod）也不起作用。
处理（开始）
开始
如果rising_edge（开始）那么
startSig
我当然知道将时钟乘以4.目前我正在使用100 MHz主时钟，但我希望最终使用400 MHz时钟进行这种插值设计，以实现0.625 ns / LSB的定时精度（1 /（4 *）
400MHz）= 1.6GHz = 0.625ns周期）。



以下为原文

Austin, thank you so much for your reply! What do you mean you would use the clock phase directly? I also tried the code below, which didn't synthesize. Using four separate processes for the clock signals to try to control one signal (startQuarterPeriod) won't work either.
 
process(start)beginif rising_edge(start) thenstartSig <= '1';end if;end process;process(clk0, clk90, clk180, clk270)beginif startSig = '1' thenif rising_edge(clk0) thenstartQuarterPeriod <= "000";end if;if rising_edge(clk90) thenstartQuarterPeriod <= "001";end if;if rising_edge(clk180) thenstartQuarterPeriod <= "010";end if;if rising_edge(clk270) thenstartQuarterPeriod <= "011";end if;end if;end process; 
I definitely understand multiplying the clock by 4. Currently I'm using the 100 MHz master clock, but the I hope to eventually use a 400 MHz clock with this interpolation design to achieve timing accuracy of 0.625 ns/LSB (1 / (4 * 400 MHz) = 1.6 GHz = 0.625 ns period).

摩根，我非常感谢你的回复！
感谢您的信息！
我只是希望他们的训练课程不那么贵！
:)



以下为原文

Morgan, I really appreciate your response! Thanks for the information! I just wish their training sessions weren't so expensive! :)

peta32387写道：
感谢您的信息！
我只是希望他们的训练课程不那么贵！
:)
你是受欢迎的...
培训看起来很昂贵，但是当一个人在一个时间紧迫的资助项目上工作时，它本身就会好几倍，培训将有助于避免时间减少挫折（满足时间，有效使用工具，创建适当的约束等）。
***我们中的许多人都是FPGA爱好者，而不是Xilinx员工。
如果您获得帮助并给予荣誉（明星），您将来可能会继续获得帮助。
如果您有解决方案，请将其标记为解决方案。***



以下为原文

 

peta32387 wrote:
Thanks for the information!  I just wish their training sessions weren't so expensive! :)

you're welcome peta...
 
Training seems expensive, but it pays for itself several times over when one is working on a funded project that is time critical, and the training will help avoid time sapping frustrations (meeting timing, using tools effectively, creating proper constraints, etc.). 
***Many of us who help you are just FPGA enthusiasts, and not Xilinx employees.  If you receive help, and give kudos (star), you're likely to continue receiving help in the future.  If you get a solution, please mark it as a solution.***

p，
我的意思是不在90,180和270 DCM_ADV输出上使用BUFG。
您可能需要实例化DCM_ADV原语，并且只对CLOCK0输出使用BUFG。
这样您就可以按原来的方式连接信号，而不会出现无法访问的路由错误。
时间可能有点奇怪（有/没有BUFG将有不同的延迟），但它应该'工作'。
Austin Lesea主要工程师Xilinx San Jose



以下为原文

p,
 
I mean to not use the BUFG on 90, 180, and 270 DCM_ADV outputs.
 
It may be you have to instantiate the DCM_ADV primitive, and only use a BUFG for the CLOCK0 output.
 
That way you should be able to connect the signals as you originally tried, without getting the unreachable routing error.
 
Timing might be a bit odd (with/without BUFG will have different delay), but it should 'work.'
 
 
 
 
Austin Lesea
Principal Engineer
Xilinx San Jose

好的 - 让我们后退一步......
暂时忘掉VHDL  - 你必须考虑硬件。
即使快速浏览参考文件，也能清楚地显示出目的是什么 - 对于时间数字转换器，您希望获得尽可能精确的“时间”度量。
正如Austin建议的那样，在FPGA中执行此操作的唯一合理方法是以尽可能高的采样率对输入信号（START）进行采样。
在任何FPGA中，内部时钟可以运行的速度存在物理限制 - 这些限制由FPGA内部时钟网络的最大速率决定。
不同的FPGA系列有不同类型的时钟网络......
因此，举一个例子，让我们在-1速度等级中使用Artix-7。
BUFG的最快频率为464MHz。
使用简单的采样，您每秒可以获得4.64亿个样本，因此获得2.155ns的时间分辨率。
然而，对于“好”的TDC，这还不够快 - 你想要更高的精度。
但是你无法提高超过这一点的时钟频率。
因此，您可以考虑在每个时钟阶段对数据进行多次采样。
要为每个内部时钟执行两个采样，只需使用内部时钟的两个边沿，并使用IDDR进行双倍数据速率采样;
IDDR是专门用于采样双倍数据速率输入信号的专用I / O单元。
这可以使用IDDR的本地反转（在超高速下具有一些潜在的占空比问题）或使用时钟上的IDDR_2CLK和采样以及时钟的180度移位版本（可以由MMCM生成）来完成
/ PLL / DCM取决于FPGA系列）。
这样做，您可以将采样率提高一倍，并将分辨率有效地减半至1.078ns。
这将为您提供每个时钟在464MHz的两个样本。
在较新的设备中，您还可以访问ISERDES。
通常，ISERDES用于SDR或DDR模式（与我上面描述的相同）。
但是，还有一种称为“过采样模式”的附加模式。
在这种情况下，您可以使用时钟的四个阶段对输入信号进行采样;
CLK0，CLK90;
CLK180;
CLK270。
这些是由MMCM或PLL（较新技术）或DCM（较旧技术）生成的。
在过采样模式下，每个时钟可获得4个信号样本;
因此有效的采样分辨率为539ps。
所有这些似乎都在参考文献中进行了描述（相当合理）。
这就是FPGA的架构功能。
现在你必须弄清楚如何使用它们。
只能使用VHDL或Verilog推断出最简单的“每个时钟一个样本”。
所有更高级的东西都需要通过直接实例化IDDR或IDDR_2CLK（每个时钟2个样本）或过采样模式下的ISERDES（每个时钟4个样本）来完成。
Avrum



以下为原文

OK - let's take a step back...
 
Forget about VHDL for the moment - you have to think hardware.
 
Even a quick glance at the referenced paper clearly shows what the intent is - for Time to Digital Converers you want to get as accurate a measure of "time" as you can get.
 
As Austin recommended, the only reasonable way to do this in an FPGA is to sample the incoming signal (START) with as high a sample rate as you can. In any FPGA, there are physical limitations to the speed the internal clock can run at - these are determined by the maximum rate of the clock network inside the FPGA. Different FPGA families have different types of clock networks...
 
So, as an example, lets take an Artix-7 in the -1 speed-grade. The fastest frequency for a BUFG is 464MHz. Using simple sampling, you can get 464 million samples per second, and hence get a time resolution of 2.155ns.
 
However, for "good" TDC, this isn't fast enough - you want more precision. But you can't increase the clock rate past that point. So, you can consider sampling the data more than once during each clock phase. To do two samples per internal clock you simply use both edges of the internal clock and use double data-rate sampling using an IDDR; the IDDR is a specialized I/O cell specifically for sampling double data rate input signals. This can either be done using local inversion at the IDDR (which has some potential duty cycle issues at super high speeds) or use the IDDR_2CLK and sample on the clock and a 180 degree shifted version of the clock (which can be generated by an MMCM/PLL/DCM depending on the FPGA family). Doing this, you double the sampling rate, and effectively halve the resolution to 1.078ns. This will give you two samples each clock at 464MHz.
 
In the newer devices, you also have access to the ISERDES. Normally the ISERDES is used in SDR or DDR mode (the same as I described above). However, there is an additional mode called "Oversample Mode". In this case, you can sample an incoming signal using FOUR phases of the clock; CLK0, CLK90; CLK180; CLK270. These are generated by an MMCM or PLL (newer technologies) or a DCM (older technologies). In Oversample mode, you get 4 samples of the signal each clock; thus an effective sampling resolution of 539ps.
 
All of this seems to be described (pretty reasonably) in the referenced paper.
 
This is what the architectural capabilities of the FPGA are. Now you have to figure out how to use them.
 
Only the simplest "one sample per clock" can be inferred using VHDL or Verilog. All the fancier things need to be done by direct instantiation of the IDDR or IDDR_2CLK (for 2 samples per clock) or the ISERDES in oversample mode (for 4 samples per clock).
 
Avrum
 
 

哦，你不能忘记亚稳态 - 通过这种方式对异步信号进行采样，你的IDDR或ISERDES会变成亚稳态。
因此，在状态机内部使用此信号确定其“时间”之前，必须让它通过适当的亚稳态分辨率电路。
这将意味着每个信号上的许多背对背触发器，以允许亚稳态解决。
这些触发器必须在Vivado中设置一个特殊属性（ASYNC_REG），或者必须在ISE中的网络上设置MAXDELAY时间约束。
在高时钟频率下，您应该考虑使用3组甚至更多组的触发器来实现亚稳态。
最后，你的计数器和比较器......等都很难以这些高时钟频率运行。
您可能希望在内部以较低的时钟速率运行设计，并在每个较低的时钟中处理多个时钟速率的样本。
因此，例如，在之前使用的Artix-7中，您可能想要考虑不是在464MHz运行您的设计，而是在232处运行您的设计并同时处理来自两个连续464MHz时钟的4个样本。
Avrum



以下为原文

Oh, and you can't forget metastability - by sampling the asynchronous signal this way, your IDDR or ISERDES will go metastable. So, before you can use this signal inside a state machine for determining its "time" you have to have it go through proper metastability resolution circuits. This will mean a number of back-to-back flip-flops on each signal to allow metastability to resolve. These flip-flops would have to have a special attribute (ASYNC_REG) set on them in Vivado, or would have to have a MAXDELAY time constraint set on the net between them in ISE. At high clock rates, you should consider 3 or even more sets of flip-flops for metastability.
 
Finally, your counters and comparators, etc... are all going to be very hard to get running at these high clock rates. You are probably going to want to run your design at a lower clock rate internally and treat multiple clock rates worth of samples in each of these lower clocks. So, for example, in the Artix-7 I used before, you would probably want to consider running your design not at 464MHz, but maybe at 232 and deal with the 4 samples from two consecutive 464MHz clocks at the same time.
 
Avrum