[问答]

为什么在verilog中添加与逻辑的其他部分无关的进程会影响输出？

问答对人有帮助，内容完整，我也想知道答案 0 为什么在verilog中添加与逻辑的其他部分无关的进程（带有always语句）会影响输出？我将该过程添加到verilog代码中，即该过程中的一个寄存器将根据状态机中的某些信号变高或变低，并且此过程中的寄存器用作包含该过程的模块的输出。输出连接到连接到测试点的FPGA引脚之一。逻辑上，状态机的输出独立于添加到代码的进程bc状态机中的信号只是正在添加的进程的输入。但是，输出与我的观察略有不同。为什么状态机的输出受到仅使用状态机中的信号和寄存器值作为输入的过程的影响？这是否与verilog转换器结合约束文件的影响有关？约束文件约束时钟信号，并且进程使用时钟。请帮帮我。对此，我真的非常感激。以上来自于谷歌翻译以下为原文 Why adding a process (with always statement) in verilog that is unrelated to the other part of logic can affect the output? I added the process to the verilog code so that one register in this process will go high or low based on certain signals in the state machine, and the register in this process is used as an ouput of the module that includes the process. The output is conncected to one of the FPGA pins that is wired to the test point. Logically, the output of state machine is independent of the process being added to the code bc the signal in the state machine is just a input to the process being added. However, the output is slightly different from my observation. Why is the output of state machine affected by the process that only uses signals and registers values in the state machine as input? Does this have to do with the verilog translator in combine with the influence of the constraint file? The constraint file constrains the clock signal and the process uses the clock. Please help me. I really appreciate it. 0
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答案对人有帮助，有参考价值 0 >>但是，输出与我的观察略有不同。你需要更具体地了解你的预期和观察结果，以便可以做出更详细的反应，但一般来说观察系统可能会改变它的行为:-)特别是在您的情况下，添加观察点可能会阻止综合工具进行一些优化并为合成输出添加更多逻辑。 - 如果提供的信息有用，请将答案标记为“接受为解决方案”。给予您认为有用且回复的帖子。以上来自于谷歌翻译以下为原文 >> However, the output is slightly different from my observation. you need to be more specific as to what you expected and observed so that a more detailed response can be made but in general observing a system may change its behavior :-) Specifically in your case, it is possible that adding an observation point is preventing the synthesis tool making some optimizations and adding more logic to the synthesized output.- Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented.

2019-3-27 07:51:05 评论举报陈苏文

答案对人有帮助，有参考价值 0 嗨Muzaffer，非常感谢您的回复。我有点惊讶的是，添加一个观察点可以改变系统的行为bc我曾经是一个C程序员：p。但我知道FPGA是非常不同的野兽。 “有可能添加一个观察点阻止综合工具进行一些优化，并为合成输出添加更多逻辑。” 这就是我认为可能导致问题的原因。合成工具的工作方式对我来说一直是个谜。我想知道如何防止或最小化由综合工具引起的这种不良影响。谢谢齐以上来自于谷歌翻译以下为原文 Hi Muzaffer, Thank you very much for your reply. I am kinda surprised that adding an observating point can change the behavior of the system bc I used to be a C programmer :p. But I know that FPGA is very different beast. "it is possible that adding an observation point is preventing the synthesis tool making some optimizations and adding more logic to the synthesized output." That is what I thought that could happen that causes the issue. The way synthesis tool works has always been a mystery for me. I would like to know how to prevent or minimize such undesirable influence causing by the synthesis tool. Thanks Qi

2019-3-27 08:08:04 评论举报李云