怎么使用多个进程编写Verilog/VHDL代码

出于模拟的目的，（而不是）是有用的复位或上电状态。
这允许您验证重置逻辑的有效性。
- 鲍勃埃尔金德
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以下为原文

For the purposes of simulation, (rather than ) is a useful reset or power-up state.  This allows you to verify the effectiveness of your reset logic.
 
-- Bob Elkind
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None


以下为原文

orenhoffmann wrote:
I would be happy to hear opinions regarding "don’t care" as reset value:
 
I have a large design, which is hard to meet timing.
Most of my modules are coded as a single synchronous process; The reset there is synchronous.
 
For many of the registers in my design, a reset value is not a must, since, for example, many of them are just some pipeline registers, accompanied by some "valid" bit (the "Valid" bits do have reset values).
I use local synchronized reset in almost any module I have.
 
As mentioned, my project has a single synchronous process per module.

I know that this is a common idiom (to write one process per entity), but I feel that in many cases the process gets unwieldy. There's a lot to be said about breaking up a large process into smaller processes, if only to increase human readability.
 
I've always had this nagging concern that if I had a synchronous process (with sync reset) and only reset some, not all, of the flops, then the tools would complain or something. I suspect that this is unfounded but I'm too lazy to do the test. So, anyway, my guess is that it's fine if the signals which do not need a reset (probably most of the signals in your design) are not reset.

I saw that if I simply do not write any reset value for some register, there still is reset fanout and logic to this register, since for this register, the ISE makes logic to "keep" the value during reset;
Hence, the reset then is either related to the "enable" port of those flip-flops, or, ISE makes a mux from the flip-flop output to its input, in order to maintain value during reset period.

Sometimes, when you code a synchronous reset, the synthesizer realizes that it can do a "better" job by looking at the rest of the logic for a particular flop and realizing that the reset condition can be easily rolled into the CE input or the D input logic.
 
And other times it may look at the code and go, "huh, that signal functions as a reset, so even though you code doesn't call it out as a reset it actually is," so the flop has its own local reset signal.
 
It's easiest if you consider that a flip-flop has three data inputs, each of which can be fed by its own cloud of combinatorial logic, and as such while you think that you're not using the reset input, the tools can choose to use it if it reduces logic elsewhere.
 
Also, "the ISE makes logic to 'keep' the value during reset," remember that reset, either synchronous or asynchronous, clears the flop output to zero; it doesn't "keep" anything.  If you want to "keep" the previous state of the flop regardless of the D input state, you deassert the CE input.

I would like to remove reset logic for all registers where it is not a must to have a reset value, in order to reduce routing resources and help meet timing.

If your code for any arbitrary flop does not include your synchronous reset signal, then that flop cannot be reset by that signal. It is as simple as that. 

I intend to write a "don't care" value as reset assignment for all those registers which is not a must to have reset value for them.
 
I made some experiment on this, and saw in the RTL and technology viewers that it seems like it makes the job:
Say we are talking about some pipeline register: in that case, if it has a "don't care" as its reset value, I saw that the ISE then completely ignores (as expected) the reset input, and only keep the main logic for that register.
 
Hence, seems like this "don't care" approach indeed help reduce reset fanout (and thus reduce routing resources and also help meet timing).

It's interesting, but in retrospect expected, that the synthesizer doesn't connect the reset signal to the flop in the case of assigning don't-care in the reset condition, but again I think that the simpler case would be to simply not involve the reset signal at all in the description of these flip-flops.
----------------------------Yes, I do this for a living.

你好，
谢谢大家的答案 ：-）
继续这些答案，我制作了一个微小的Verilog模块，测试这里提到的所有4个复位选项。
代码只是一个管道256位寄存器，伴随有效输出。
我不关心256位输出复位值，因为“有效”输出将在有效时显示。
1.正常复位为“out1”输出：
代码：
`timescale 1ns / 1ps
module reset_test
（ 
输入clk， 
输入rst， 
输入[255：0] in1， 
输出reg [255：0] out1， 
输出reg out1_valid
）; 
（* KEEP =“TRUE”*）reg [1：0] rst_local;
/ *******************
********************* /
//将重置同步到本地时钟：
/ *******************
********************* / 
总是@（posedge clk）开始 
rst_local [1：0]
2.未指定复位指定为“out1”输出：相关代码： 
总是@（posedge clk）开始 
if（rst_local [1]）开始 
//“out1”没有重置值。 
out1_valid
3.将复位逻辑移至底部，在选定的寄存器上：相关代码： 
总是@（posedge clk）开始 
out1 4.重置值为“out1”定义为unknown /不关心：相关代码： 
总是@（posedge clk）开始 
if（rst_local [1]）开始 
OUT1
所以底线，我看到我们得到了与选项3和4相同的结果：没有复位扇出到“out1”输出寄存器。
我认为对于我的项目，我更喜欢选项4而不是3，因为：
- 在选项3中，我们必须记住，现在和将来，不要在重置部分下面写任何东西，它必须位于过程的最低位置。
- 在选项4中，可以更直观地看出哪个寄存器具有已定义的复位值，哪个具有未知/无关复位值。



以下为原文

Hello,
 
Thank you all for your answers :-)
 
In continuation to those answers, I made a tiny Verilog module, to test all 4 options for reset mentioned here.
The code is just a pipeline 256 bit register, accompanied by a valid output.
I don't care about the 256 bit output reset value, since the "valid" output will show when it is valid.
 
 1.    With normal reset to "out1" output:
 
The code:
 
`timescale 1ns / 1ps
 
module reset_test
(
            input clk,
            input rst,
 
            input [255:0] in1,
           
            output reg [255:0] out1,
            output reg out1_valid
 
);
 
            (*KEEP="TRUE"*) reg [1:0] rst_local;           
           
/**********************************************************************/
// Sync the reset to local clock:
/**********************************************************************/
            always @(posedge clk) begin
                        rst_local[1:0] <= { rst_local[0] , rst };
            end
           
/**********************************************************************/
// The main logic:
/**********************************************************************/
            always @(posedge clk) begin
                        if(rst_local[1]) begin
                                    out1 <= 0;
                                    out1_valid <= 0;
                        end
                        else begin
                                    out1 <= in1;    
                                    out1_valid <= 1;                                                                                             
                        end                 
            end     
endmodule
 


            The result:
 

2. Without reset specified to "out1" output:

The relevant code:


            always @(posedge clk) begin
                        if(rst_local[1]) begin
                                    // No reset value for "out1".
                                    out1_valid <= 0;
                        end
                        else begin
                                    out1 <= in1;    
                                    out1_valid <= 1;                                                                                             
                        end                 
            end    
 
The result:
Please note the connection of the reset to the "CE" of "out1" register.


3. With the reset logic moved to the bottom section, on selected registers:

The relevant code:


            always @(posedge clk) begin
                        out1 <= in1;    
                        out1_valid <= 1;                                                                                             
 
                        if(rst_local[1]) begin
                                    out1_valid <= 0;
                        end
 
            end     

The result:
4. The reset value to "out1" defined as unknown / don't care:

The relevant code:


            always @(posedge clk) begin
                        if(rst_local[1]) begin
                                    out1 <= 'bx;
                                    out1_valid <= 0;
                        end
                        else begin
                                    out1 <= in1;    
                                    out1_valid <= 1;                                                                                             
                        end                 
            end     
 
The result:

 
 
So bottom line, I see that we got the same results for options 3 and 4 : no reset fanout there to the "out1" output register.

I think that for my project, I will prefer option 4 over 3, since:
-          In option 3 we must remember, now and in the future, not to write anything below the reset section, which must be at the lowest location of the process.
-          In option 4 it could be more visually seen which register has a defined reset value and which one has an unknown / don't care reset value.
 

我想我知道发生了什么。
这些工具正在完成您告诉他们要做的事情。
请参阅上面的解释。
但让我们来看看这个具体的例子。 
总是@（posedge clk）开始 
if（rst_local [1]）开始 
OUT1 
out1_valid 
结束 
别的开始 
OUT1 
out1_valid 
结束 
结束
注意当reset为true时out1_valid如何分配给0，如果不为则分配给1。
你实际上描述了注册的逆变器。
不要调用重置信号rst_local [1]，而是将其称为foo。
你期待吗？ 
总是@（posedge clk）开始 
如果（foo）开始 
out1_valid 
结束 
别的开始 
out1_valid 
结束 
结束
推断翻牌圈foo的重置？
如果是这样，为什么？
合成器完全正确。
----------------------------是的，我这样做是为了谋生。



以下为原文

I think I see what's happening. The tools are doing exactly what you're telling them to do. See my explanation above. But let's look at this concrete example.
 
   always @(posedge clk) begin
       if (rst_local[1]) begin
           out1       <= 0;
           out1_valid <= 0;
       end
       else begin
           out1       <= in1;    
           out1_valid <= 1;                                                                                             
       end                 
    end     
 
Note how out1_valid is assigned to 0 when the reset is true, and assigned to 1 when it's not. 
You actually described a registered inverter. Instead of calling the reset signal rst_local[1], call it foo. Would you expect 
 
   always @(posedge clk) begin
       if (foo) begin
           out1_valid <= 0;
       end
       else begin
           out1_valid <= 1;
       end
    end
 
to infer a reset on the flop foo? If so, why?
 
The synthesizer did exactly the right thing.
----------------------------Yes, I do this for a living.

至于第二个例子：
总是@（posedge clk）开始 
if（rst_local [1]）开始 
//“out1”没有重置值。 
out1_valid 
结束 
别的开始 
OUT1 
out1_valid 
结束
结束
同样，您正在调用复位的信号不会作为out1向量的重置。
查看启用时钟的触发器的模板。
就是这样。
当条件为真时，触发器的Q输出从其D输入分配。
当该条件为假时，Q输出保留其值。
重新编写上面的代码并重命名rst_local以启用。
总是@（posedge clk）开始 
if（启用）开始 
OUT1 
结束
结束
这看起来像一个启用时钟的触发器吗？
是的，确实如此，这就是工具的构建。
----------------------------是的，我这样做是为了谋生。



以下为原文

As for the second example:
 
always @(posedge clk) begin
    if (rst_local[1]) begin
        // No reset value for "out1".
        out1_valid <= 0;
    end
    else begin
        out1 <= in1;
        out1_valid <= 1;
    end
end
 
Again, the signal you're calling a reset isn't acting as a reset for the out1 vector. 
 
Look at the template for a clock-enabled flip-flop. It's simply this. When a condition is true, the flop's Q output is assigned from its D input. When that condition is false, the Q output retains its value.
 
Re-write your code above and rename rst_local to enable.
 
always @(posedge clk) begin
    if (enable) begin
        out1 <= in1;
    end
end
 Does that look like a clock-enabled flip-flop? Yes, it does, and that's what the tools built.
----------------------------Yes, I do this for a living.

您的选项3实际上与其他选项不同。
总是@（posedge clk）开始 
OUT1 
out1_valid 
if（rst_local [1]）开始 
out1_valid 
结束
结束
赋值out1超出了“重置”测试。
两个赋值（out1和out1_valid）很可能位于单独的always块中。
他们是完全独立的。
而且，这些工具完全正确：out1只是in1的注册副本，并且在out1_valid上推断出逆变器（参见选项1）。
----------------------------是的，我这样做是为了谋生。



以下为原文

Your option 3 is actually different from the other options.
 
always @(posedge clk) begin
    out1       <= in1;
    out1_valid <= 1;
 
    if (rst_local[1]) begin
        out1_valid <= 0;
    end
end
 
The assignment out1 <= in1; is outside of the "reset" test. The two assignments (to out1 and to out1_valid) could well be in separate always blocks. They are entirely independent. And again, the tools did exactly the right thing: out1 is just a registered copy of in1, and an inverter is inferred (see option 1) on out1_valid.
 
 
----------------------------Yes, I do this for a living.

最后，选项4： 
总是@（posedge clk）开始 
if（rst_local [1]）开始 
out1被断言，out1确实会在显示中显示为所有'X'。
但是，由于真正的硬件不能有无关紧要的输出，它必须分配一些东西。
但是既然你已经明确地说过“我不关心你做什么”，它就能做到最简单的事情，那就是一直把输入分配给输出。
无论如何，所有这一切的关键在于工具正在创建完全符合您所描述的逻辑。
一个人编写代码并查看合成器对它的作用绝对是值得的，然后理解它为什么会这样做。
----------------------------是的，我这样做是为了谋生。



以下为原文

Finally, option 4:
 
 
   always @(posedge clk) begin
                        if(rst_local[1]) begin
                                    out1 <= 'bx;
                                    out1_valid <= 0;
                        end
                        else begin
                                    out1 <= in1;    
                                    out1_valid <= 1;                                                                                             
                        end                 
            end     
 
This is somewhat interesting, but easily explained.
 
Note the reality of the simulation/synthesis mismatch. In a simulation, whenever rst_local is asserted, out1 will indeed show in the display as all 'X'. But since real hardware cannot have a don't-care output, it has to assign something. But since you've explicitly said, "I don't care what you do," it does the easiest thing it can, which is to just assign the input to the output all the time.
 
Anyways, the point of all of this is that the tools are creating the logic that is EXACTLY what you've described. It's definitely worthwhile for one to write code and see what the synthesizers does with it, and then understand why it did what it did.
 
----------------------------Yes, I do this for a living.

那很有意思。
我仍然喜欢选项3（我建议的那个），因为很容易忘记在重置条件下将赋值添加到x，并且它允许代码缩进一级。
它也适用于异步复位，例如，如果将复位逻辑放入本地过程，则可以添加一些额外的代码以允许在异步和同步复位之间切换。
虽然我感兴趣的是'x'的做法，而不是将其分配给'0'。



以下为原文

That's interesting.  I still like option 3 (the one I suggested), because it's easy to forget to add the assignments to x in the reset conditions, and it allows the code to be indented one level less.  It also is adaptable to async resets, eg if you put the reset logic into a local procedure, you can put some extra code in to allow switching between async and sync resets.
 
Though I am interested in the assignemnt to 'x' doing something other than assigning it to '0'.

cdstahl_personal写道：
那很有意思。
我仍然喜欢选项3（我建议的那个），因为很容易忘记在重置条件下将赋值添加到x，并且它允许代码缩进一级。
它也适用于异步复位，例如，如果将复位逻辑放入本地过程，则可以添加一些额外的代码以允许在异步和同步复位之间切换。
我想这归结为你喜欢的风格。
您的代码没有任何问题。
虽然我感兴趣的是'x'的做法，而不是将其分配给'0'。
这是上面解释的。
请记住，'X'意味着你不在乎，合成器将始终做最简单的事情。
最简单的是一个简单的D触发器，没有复位，也没有时钟使能。
这就是它的作用。
如果你想让它重置为'0'，那么你必须编码。
注意：在std_logic中，'X'并不是一个小心点。
它强迫未知，可以指定的最高强度值。
' - '不在乎。
----------------------------是的，我这样做是为了谋生。



以下为原文

cdstahl_personal wrote:
That's interesting.  I still like option 3 (the one I suggested), because it's easy to forget to add the assignments to x in the reset conditions, and it allows the code to be indented one level less.  It also is adaptable to async resets, eg if you put the reset logic into a local procedure, you can put some extra code in to allow switching between async and sync resets.

I suppose it comes down to your preferred style. There's nothing wrong with your code.

Though I am interested in the assignemnt to 'x' doing something other than assigning it to '0'.

That's explained above. Remember, 'X' means you don't care, and the synthesizer will always do what's easiest. The easiest thing is a simple D-flip-flop with no reset and no clock enable. And that's what it did.
 
If you want it to reset to '0' then that's what you must code.
 
NB: In std_logic, 'X' isn't a don't-care. It's forcing unknown, the highest strength value one can assign. '-' is don't care.
----------------------------Yes, I do this for a living.