可以将3.3VLVTTL信号连接到3.3V CMOS输入电路吗？

如果您发布了代码，我们可能会为您提供更多直接帮助。
因为它与你提供的信息一致，我们都只是在猜测。
我的第一个猜测：您使用什么频率的时钟来检测输入信号的上升沿？
输入信号是否与此时钟正确同步？
----------“我们必须学会做的事情，我们从实践中学习。”
- 亚里士多德



以下为原文

May be if you posted your code, we'd be able to give you more direct assistance. As it stands with the information you've provided, we're all just guessing.
 
For my first guess: what frequency of clock are you using to detect the incoming signal's rising edge? Is the incoming signal correctly synchronised to this clock?
----------
"That which we must learn to do, we learn by doing." - Aristotle

嗨，
你只检查过行为模拟吗？
检查所有后期综合和后期实施模拟，您可能会知道哪里出错了。
在比较所有三种模拟时，检查FSM变量的变化，即下一个状态和当前状态。这是它可能不匹配的最大可能性。
希望这可以帮助
谢谢
Shreyas
--------------------------------------------------
--------------------------------------------请注意 - 请注明
如果提供的信息有用，请回答“接受为解决方案”。
将Kudos发送给您认为有用且回复的帖子.------------------------------------
--------------------------------------------------
--------
--------------------------------------------------
--------------------------------------------尝试搜索你的答案
在发布新帖子之前在论坛或xilinx用户指南中发出问题。请注意 - 如果提供的信息解决了您的问题，请将答案标记为“接受为解决方案”。给予您认为有用的帖子给予荣誉（右边提供的星号）
并回复.----------------------------------------------
------------------------------------------------



以下为原文

Hi,
 
Have you checked only behavioral simulation?
check all post synthesis and post implementation simulation, you might get an idea where is it going wrong.
while comparing all three simulations, check for variations in your FSM variables i.e. next state and current state.that is maximum possibility where it can mismatch.
 
hope this helps
 
Thanks 
Shreyas
 
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------
Try to search answer for your issue in forums or xilinx user guides before you post a new thread.

Kindly note- Please mark the Answer as "Accept as solution" if information provided solves your query.
Give Kudos (star provided in right) to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------

嗨，
从数据表的特性看，我们可以接口LVTTL，LVCMOS。
但是我会建议你在继续之前进行IO模拟。
当你说时钟的第5个上升沿时，这是否意味着时钟的周期为1秒？
你能展示模拟输出和代码，以便我更容易理解。
Chipscope的结果是什么？
查看chipcope以了解它出错的地方。
谢谢，AnirudhPS：请将此标记作为答案，以防它有助于解决您的问题。如果帖子引导您找到解决方案，请给予赞誉。



以下为原文

Hi,
 
From the datasheet characteristics it looks like we can interface LVTTL, LVCMOS. However i would recommend you to do IO simulation before proceeding.
 
When you say 5th rising edge of the clock, does that mean the period of the clock is 1 sec? Can you show the simulation output and the code so that i should be easier to understand.
 
What is the result in Chipscope? CHeck in chipscope to know where it is going wrong.
 
 
Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.

我只做过行为模拟。
我在50MHz时钟运行。
输入脉冲在第二个开始时具有20us宽的上升沿。
1PPS synch reset.txt 2 KB



以下为原文

I have only done beharvioral simulation. I am running at 50MHz clock. Input pulse is have 20us wide rising edge at the start of second.
            1PPS synch reset.txt ‏2 KB

您确定您的FSM正确重置吗？
----------“我们必须学会做的事情，我们从实践中学习。”
- 亚里士多德



以下为原文

Are you sure that your FSM is being reset properly?
----------
"That which we must learn to do, we learn by doing." - Aristotle

我真正的意思是，你能确定当你释放重置时FSM处于你认为应该是的状态吗？
确切地说，FSM的重置源自何处？
如果它在模拟中运行良好，则需要使用其他形式的调试（如chipscope）来查看逻辑并查看发生的情况。
----------“我们必须学会做的事情，我们从实践中学习。”
- 亚里士多德



以下为原文

What I really meant was, can you be sure that the FSM is in the state you believe it should be when you release the reset?
 
Precisely where does the reset to the FSM originate?
 
If it all works nicely in simulation, you'll need to use some other form of debug (like chipscope) to look into the logic and see what is happening.
----------
"That which we must learn to do, we learn by doing." - Aristotle

Chipscope不是XILINX ISE工具包的一部分。
我需要单独购买它。



以下为原文

Chipscope is not part of XILINX ISE tool kit right. I need to purchase it seperately.
 

sunimal123写道：
Chipscope不是XILINX ISE工具包的一部分。
我需要单独购买它。
是。
----------------------------是的，我这样做是为了谋生。



以下为原文

sunimal123 wrote:
Chipscope is not part of XILINX ISE tool kit right. I need to purchase it seperately.
 

Yes.
----------------------------Yes, I do this for a living.