MMCM是否适用于40 Mhz或其他输入时钟？

看起来不像......
对于V6，fVCOMIN在所有速度等级中都是600MHz。
fVCOMAX在-1速度级别为1200MHz，在-3级时高达1600MHz。
所以，-3速度等级几乎不会成功;
将CLKFBOUT_MULT_F和CLKOUT0_DIVIDE_F都设置为16（这是向导在-3速度等级中输入100MHz时可能会做的事情）。
这在100MHz时提供1600MHz VCO频率，在40MHz时提供640MHz VCO。
（但我怀疑你使用的是-3速度等级）。
在-2，你不能这样做，你可以做的最大乘数是14（在100MHz时1400MHz），这将导致40MHz时fVCO为560MHz，低于fVCOMIN。
如果您需要在没有-3速度等级的情况下适应整个范围，则可能需要采用动态重新配置。
假设您知道时钟速率（或至少是范围），您可以使用MMCM的DRP端口重新编程MMCM中的分频器。
您可能只需要两组值（一组用于高端，一组用于低端），但是当您在它们之间进行转换时，您需要一个小型状态机来通过DRP更改编程，重置MMCM并让它
锁定新的分隔线。
Avrum
在原帖中查看解决方案



以下为原文

It doesn't look like it...
 
For the V6, the fVCOMIN is 600MHz in all speed grades. The fVCOMAX is 1200MHz in the -1 speed grade, up to 1600MHz, in the -3. So, the -3 speed grade will just barely make it; set both CLKFBOUT_MULT_F and CLKOUT0_DIVIDE_F to 16 (which is what the wizard would likely do with a 100MHz input in a -3 speed grade). This gives a 1600MHz VCO frequency at 100MHz, and a 640MHz VCO at 40MHz. (But I doubt you are using a -3 speed grade). At -2, you can't do it, the maximum multiplier you could do is 14 (1400MHz at 100MHz), which would result in a fVCO of 560MHz at 40MHz, which is below fVCOMIN.
 
If you need to accommodate the entire range without a -3 speed grade part, you may have to resort to dynamic reconfiguration. Assuming you know what the clock rate is (or at least the range), you can re-program the divders in the MMCM using the DRP port of the MMCM. You would probably only need two sets of values (one for the high end and one for the low end), but as you transition between them, you would need a little state machine to change the programming via DRP, reset the MMCM and let it lock with the new dividers.
 
Avrum
 
View solution in original post

嗨，您可以动态更改MMCM的输入频率，前提是新输入频率在允许的范围内，并且FVCO也应该在支持的范围内。您可以从设备数据表中找到这两个范围。另外，每次你
更改MMCM的输入时钟，建议复位MMCM并确保LOCK变为高电平。确保设计满足最新时钟频率的时序是一个好习惯。
为此，您需要更改ucf文件中的句点约束.Regards，Krishna
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以下为原文

Hi,

You can dynamically change the input frequency of the MMCM provided the new input frequency is within the allowable range and also the FVCO should also be in the supported range.

You can find both these ranges from the device datasheet.

Additionally, each time you change the input clock of MMCM, it is recommended to reset the MMCM and ensure that the LOCK goes HIGH.

It is a good practice to make sure that the design meets timing with the latest clock freq as well. To do this, you need to change  the period constraint in the ucf file.

Regards,
Krishna-----------------------------------------------------------------------------------------------
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查看器件系列（Virtex 6？）的数据手册，查找器件的VCOmin和VCOmax范围。
如果VCOmax与VCOmin的比率至少为2.5：1（100：40），那么您应该能够生成正确的参数，以允许MMCM在整个输入范围内运行。
如果没有，您可能需要使用动态重配置端口来更改参数，以使VCO频率在范围内。
我使用时钟向导完成的一件事是首先配置一个带有两个输入的MMCM，然后给它们所需范围两端的频率，在这种情况下，这将是100 MHz和40 MHz。
然后向导将尝试创建参数，使它们适用于两个输入。
如果您首先输入100 MHz作为主时钟输入，那么您将看到辅助时钟输入的有效范围。
如果该范围包括40 MHz，您应该能够做到你想要的。
-  Gabor



以下为原文

Look in the data sheet for your device family (Virtex 6?) to find the VCOmin and VCOmax range of your part.  If the ratio of VCOmax to VCOmin is at least 2.5 : 1 (100 : 40) then you should be able to generate the correct parameters to allow the MMCM to run over the whole input range.  If not, you might need to use the Dynamic Reconfiguration Port to change the parameters so that the VCO frequency is within range.
 
One thing I've done with the clocking wizard is to start by configuring an MMCM with two inputs, and give them the frequencies of the two ends of the required range, in your case this would be 100 MHz and 40 MHz.  Then the wizard will attempt to create the parameters such that they work for both inputs.  If you start by entering 100 MHz for the primary clock input, then you will see the valid range for the secondary clock input.  If that range includes 40 MHz you should be able to do what you want.
-- Gabor

看起来不像......
对于V6，fVCOMIN在所有速度等级中都是600MHz。
fVCOMAX在-1速度级别为1200MHz，在-3级时高达1600MHz。
所以，-3速度等级几乎不会成功;
将CLKFBOUT_MULT_F和CLKOUT0_DIVIDE_F都设置为16（这是向导在-3速度等级中输入100MHz时可能会做的事情）。
这在100MHz时提供1600MHz VCO频率，在40MHz时提供640MHz VCO。
（但我怀疑你使用的是-3速度等级）。
在-2，你不能这样做，你可以做的最大乘数是14（在100MHz时1400MHz），这将导致40MHz时fVCO为560MHz，低于fVCOMIN。
如果您需要在没有-3速度等级的情况下适应整个范围，则可能需要采用动态重新配置。
假设您知道时钟速率（或至少是范围），您可以使用MMCM的DRP端口重新编程MMCM中的分频器。
您可能只需要两组值（一组用于高端，一组用于低端），但是当您在它们之间进行转换时，您需要一个小型状态机来通过DRP更改编程，重置MMCM并让它
锁定新的分隔线。
Avrum



以下为原文

It doesn't look like it...
 
For the V6, the fVCOMIN is 600MHz in all speed grades. The fVCOMAX is 1200MHz in the -1 speed grade, up to 1600MHz, in the -3. So, the -3 speed grade will just barely make it; set both CLKFBOUT_MULT_F and CLKOUT0_DIVIDE_F to 16 (which is what the wizard would likely do with a 100MHz input in a -3 speed grade). This gives a 1600MHz VCO frequency at 100MHz, and a 640MHz VCO at 40MHz. (But I doubt you are using a -3 speed grade). At -2, you can't do it, the maximum multiplier you could do is 14 (1400MHz at 100MHz), which would result in a fVCO of 560MHz at 40MHz, which is below fVCOMIN.
 
If you need to accommodate the entire range without a -3 speed grade part, you may have to resort to dynamic reconfiguration. Assuming you know what the clock rate is (or at least the range), you can re-program the divders in the MMCM using the DRP port of the MMCM. You would probably only need two sets of values (one for the high end and one for the low end), but as you transition between them, you would need a little state machine to change the programming via DRP, reset the MMCM and let it lock with the new dividers.
 
Avrum
 

有趣。
我的旧版V6数据表显示所有速度等级的VCOmin均为400 MHz，这意味着任何V6都可以做到这一点。
顺便说一句，我刚刚对Kintex-7设计进行了这项练习，其VCO范围（比例）比V6更低。
我不得不将MMCM编程分解为三个范围，以获得20-85 MHz的输入频率。
范围有一些重叠，这允许状态逻辑在确定范围时具有一些滞后。
当输入频率处于范围切换阈值时，这可以防止来回切换。
状态逻辑在另一个具有恒定频率的时钟上运行 - 这也是测量可变时钟输入的输入频率所必需的。
我在全局时钟缓冲器上也运行不足，在设计中有许多接口。
我将输入时钟没有缓冲到单个触发器中，以创建输入频率的1/2。
然后在恒定时钟上对该半频信号进行采样，以找到输入频率/ 2。
-  Gabor



以下为原文

Interesting.  My old V6 data sheet shows VCOmin at 400 MHz for all speed grades, which would have meant any V6 could do it.
 
By the way I've just gone through this very exercise on a Kintex-7 design which has even less VCO range (as a ratio) than the V6.  I had to break up my MMCM programming into three ranges to get the 20-85 MHz input frequency.  The ranges had a bit of overlap which allows the state logic to have some hysteresis in determining the range.  This prevents switching back and forth when the input frequency is at the range switch threshold.  The state logic runs on another clock that has a constant frequency - also necessary to measure the input frequency of the variable clock input.  I was also running low on global clock buffers, having a number of the interfaces in the design.  I took the input clock without buffering it into a single toggle flop to create 1/2 the input frequency.  Then that half-frequency signal was sampled on the constant clock to find the input frequency / 2.
-- Gabor

嗨，
这是一个AR，它应该为这个主题添加更多信息-http：//www.xilinx.com/support/answers/37806.html
对于动态重新配置，有一个带有7系列的XAPP。
您可以从中获取线索以帮助您的案例。
谢谢，AnirudhPS：请将此标记作为答案，以防它有助于解决您的问题。如果帖子引导您找到解决方案，请给予赞誉。



以下为原文

Hi,
 
Here is one AR which should add further information to this topic - http://www.xilinx.com/support/answers/37806.html
 
For dynamic reconfiguration there is an XAPP with 7 series. You can take cues from this to help with your case.
 
 
Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.