MMCM锁定信号行为

不确定你的意思是10MHz的变化（我假设输入时钟）？
如果是这样，请确保您不会违反数据表中的MMCM规范所导致的任何变化。



以下为原文

Not sure what you mean by variations of 10MHz (I presume the input clock)? If so, make sure you don't violate any af the MMCM specs in the data sheet cause by those variations..

谢谢，我将研究PLL的抖动特性。
但是，我定义MMCM的输入/输出频率是不是一个问题，这与DDS给出的不完全相同？



以下为原文

Thank you, i will look into the jitter characteristics of the PLL. But is it not a problem that i define my input/output frequencies of the MMCM which are not exact to what the DDS gives out?

但是，我定义MMCM的输入/输出频率是不是一个问题，这与DDS给出的不完全相同？
它可能是，但它取决于频率范围......
时钟向导期望一个简单的固定“CLKIN”产生一组CLKOUT频率。
它使用这些来确定和编程MMCM内部乘法器和分频器的“理想”设置。
但是，MMCM只不过是一个倍频器和分频器。
因此，如果您的CLKIN与您指定的不同（比如低10％），那么您的输出也将降低10％。
但是...... MMCM中有许多特性不得违反 - 主要是VCO和PFD的最小和最大频率，两者都在DS181表37中定义。最小值到最大值的范围
这些都非常大（VCO超过2：1，PFD更宽）。
因此，如果您接近这些范围的中间，10％将无法发挥作用。
但是，如果用于配置MMCM的频率将其中一个置于极限附近（通常是VCO最大值），然后你超过指定的输入频率以推动VCO超过VCOMAX，那么你也可能失去锁定......
如果是这样，那么您需要对MMCM的乘法器和除法器进行不同的编程，以便最终得到的设置对您期望的最大和最小输入频率都有效。
如果您可能的输入频率范围很小，那么这应该是可行的。
Avrum



以下为原文

But is it not a problem that i define my input/output frequencies of the MMCM which are not exact to what the DDS gives out?
 
It may be, but it depends on the range of frequencies...
 
The clocking wizard expects a simple fixed "CLKIN" generating a set of CLKOUT frequencies. It uses these to determine and program the "ideal" settings for the MMCM's internal multipliers and dividers. However, the MMCM is nothing more than a frequency multiplier and divider. So if your CLKIN is different than what you specified (say 10% lower) then your outputs will also be 10% lower.
 
BUT... There are a number of characteristics within the MMCM that must not be violated - mostly the minimum and maximum frequencies of the VCO and the PFD, both of which are defined in DS181 table 37. The ranges on the min to max of these are pretty large (more than 2:1 for the VCO and much wider for the PFD). So if you are near the middle of these ranges, 10% won't make a difference.
 
However, if the frequencies you use to configure the MMCM place one of these near the limit (usually the VCO max) and then you go enough above the specified input frequency to push the VCO past VCOMAX, then you can also lose lock...
 
If so, then you need to program the multipliers and dividers of the MMCM differently so that you end up with the settings being valid for both the maximum and minimum input frequencies you expect. If the range on your possible input frequencies is small, then this should be doable.
 
Avrum

我检查了IP核摘要，乘数值是8.我的F0 * 8是根据数据表在VCOmax的中间范围，所以我认为这不会产生问题。
但是，有一个规范 -  MMCM_RST_MINPULSE = 5 ns。
这是否意味着我必须在启动时重置我的MMCM至少5 ns。
我目前已将复位引脚连接到0，这意味着我从未重置MMCM ...



以下为原文

I checked the IP core summary, and the multiplier value is 8. my F0*8 is in the mid-range of VCOmax as per the datasheet, so i assume this would not create problems. However, there is a specification - MMCM_RST_MINPULSE = 5 ns. Does this mean i have to reset my MMCM on bootup for a minimum of 5 ns. I have currently connected the reset pin to 0, meaning i never reset the MMCM...

但是，有一个规范 -  MMCM_RST_MINPULSE = 5 ns。
这是否意味着我必须在启动时重置我的MMCM至少5 ns。
我目前已将复位引脚连接到0，这意味着我从未重置MMCM ...
作为FPGA配置过程的一部分，MMCM保持复位状态。
如果在FPGA配置期间输入时钟存在并且稳定，那么这对于初始复位就足够了（并且可以将RST引脚连接到0）。
但是，如果在初始复位后，输入时钟不存在，或者在MMCM可以跟踪的频率或相位之外改变频率或相位，则MMCM将不会锁定或将失锁。
如果发生这种情况，那么一旦有了稳定的输入时钟，就需要明确地重置MMCM。
Avrum



以下为原文

However, there is a specification - MMCM_RST_MINPULSE = 5 ns. Does this mean i have to reset my MMCM on bootup for a minimum of 5 ns. I have currently connected the reset pin to 0, meaning i never reset the MMCM...
 
As part of the configuration process of the FPGA, the MMCM is held in reset. If the input clock is present and stable during the FPGA configuration, then this is sufficient for the initial reset (and you can tie the RST pin to 0). However, if, after this initial reset, the input clock is not present, or changes frequency or phase outside of what the MMCM can track, then the MMCM will not lock or will lose lock. If this happens, then you need to explicitly reset the MMCM once you have a stable input clock.
 
Avrum

可能这是我的问题。
在启动时配置FPGA后，我编写了Microblaze以与DDS进行通信以配置DDS。
只有在配置DDS之后，才能为MMCM获得稳定的输入时钟。
配置完DDS后，我会重置DCM，然后重试。
非常感谢你



以下为原文

probably this is my problem. After the FPGA is configured on bootup, I have programmed Microblaze to perform communication to the DDS to configure the DDS. Only after the DDS is configured, I can get a stable input clock to the MMCM. I will reset the DCM once DDS is configred, and try again. Thank you very much