时钟域跨越fifo时间失败

所以，甚至更好。
在8：1反序列化中使用ISERDES（在DDR模式下）。
对于8个数据位中的每一个，这将导致每个周期在139MHz的8位数据（在139MHz时每个时钟总共64位）。
将其中的4个组合在一起得到256位字，并将它们写入FIFO。
这样，只有ISERDES的高速侧运行在556MHz  -  ISERDES的低速侧以及将这些字组合在一起得到256位并将它们写入FIFO的逻辑运行在139MHz。
在这些速度下，FIFO逻辑不会出现任何问题。
高速接口的目标是尽快让它们“缓慢而宽阔”;
具有最少量的逻辑以高时钟速度运行。
Avrum
在原帖中查看解决方案



以下为原文

So, even better.
 
Use the ISERDES in 8:1 deserialization (in DDR mode). This will result in 8 bits of data every cycle at 139MHz for each of your 8 data bits (for a total of 64 bits per clock at 139MHz). Combine 4 of these together to get your 256 bit word and write them to the FIFO.
 
This way, only the high speed side of the ISERDES is running at 556MHz - the low speed side of the ISERDES and the logic to combine the words together to get 256 bits and write them to the FIFO is running at 139MHz. At these speeds you won't have any problems with the FIFO logic.
 
The goal with high speed interfaces is to get them "slow and wide" as soon as possible; have the least amount of logic running at the high clock speed.
 
Avrum
View solution in original post

你好
跨时钟域应用了最大延迟约束。
请参阅此处的快照。
--Hem
--------------------------------------------------
--------------------------------------------请注意 - 请注明
如果提供的信息有用，请回答“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢K--
--------------------------------------------------
---------------------



以下为原文

Hi
 
There are max-delay constraints applied to cross clock domains. Refer to the snapshot here.
 
--Hem
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------

你用的是什么工具？
你使用什么限制？
FIFO是如何生成的？
使用的属性是什么？
什么是实际的时间故障？
没有细节，我们无法给出有意义的答案。
Avrum



以下为原文

What tool are you using? What constraints are you using? How was the FIFO generated? What were the attributes used? What is the actual timing failure?
 
Without details we can't give meaningful answers.
 
Avrum

取决于时序故障的位置。
如果它们在550-> 550或150-> 150路径上，则需要通过常规时序闭合方法来修复它们。
另一方面，如果它们在550-> 150和/或150-> 550路径上，如果这两个时钟是异步的，因为你在帖子中提到“CDC”，那么就没有办法真正修复这些违规行为，因为
时钟漂移。
这就是为什么需要良好的CDC方法。
- 如果提供的信息有用，请将答案标记为“接受为解决方案”。给予您认为有用且回复的帖子。



以下为原文

Depends on where the timing failures are. If they are on 550->550 or 150->150 paths, you need to fix them by regular timing closure methods. On the other hand, if they are on 550->150 and/or 150->550 paths and if these two clocks are asynchronous as you mention "CDC" in your post, then there is no way to actually fix these violations because of clock drift. That's why one needs good CDC methodology.- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

你用的是什么工具？
你使用什么限制？
FIFO是如何生成的？
使用的属性是什么？
什么是实际的时间故障？
我正在使用vivado 2013.3和fifo是使用fifo生成器生成的（ind时钟分布式ram，本机接口，同步级= 2，启用重置同步，写入宽度256，写入深度17，异步重置）
使用以下约束。
我使用create_clock来定义556 Mhz clk
set input_clock clk_556;
＃输入时钟集名称input_clock_period 1.797;
＃输入时钟周期（全周期）设置dv_bre 0.01044925;
＃数据在上升时钟edgeset之前有效dv_are 0.01044925;
＃上升时钟边沿后的数据有效dv_bfe 0.01044925;
＃数据在下降时钟edgeset之前有效dv_afe 0.01044925;
＃数据在下降时钟edgeset后有效input_ports [list data0_p data1_p data2_p data3_p data4_p data5_p data6_p data7_p];
＃输入端口列表
#Input Delay Constraintset_input_delay -clock $ input_clock -max [expr $ input_clock_period / 2  -  $ dv_bfe] [get_ports $ input_ports]; set_input_delay -clock $ input_clock -min $ dv_are [get_ports $ input_ports]; set_input_delay -clock $ input_clock -max [expr
$ input_clock_period / 2  -  $ dv_bre] [get_ports $ input_ports] -clock_fall -add_delay; set_input_delay -clock $ input_clock -min $ dv_afe [get_ports $ input_ports] -clock_fall -add_delay;
失败路径作为图片附加。
当我给出命令report_compile_order -constraints时，tcl控制台只显示我添加的一个xdc文件。
它没有显示fifo生成的xdc文件。
那些xdc文件确实有set_max_delay和set_false_path约束，但我不认为xilinx正在接受它们。
我必须手动添加它们吗？



以下为原文

What tool are you using? What constraints are you using? How was the FIFO generated? What were the attributes used? What is the actual timing failure?
 
I am using vivado 2013.3 and fifo was generated using fifo generator(ind clocks distributed ram, native interface,sync stages =2 , enable reset sync, write width 256, write depth 17, async reset)
 
using following constraints.
i am using create_clock to define 556 Mhz clk
 
set input_clock         clk_556;            # Name of input clock
set input_clock_period  1.797;         # Period of input clock (full-period)
set dv_bre              0.01044925;        # Data valid before the rising clock edge
set dv_are              0.01044925;        # Data valid after the rising clock edge
set dv_bfe              0.01044925;        # Data valid before the falling clock edge
set dv_afe              0.01044925;        # Data valid after the falling clock edge
set input_ports         [list data0_p data1_p data2_p data3_p data4_p data5_p data6_p data7_p];     # List of input ports
# Input Delay Constraint
set_input_delay -clock $input_clock -max [expr $input_clock_period/2 - $dv_bfe] [get_ports $input_ports];
set_input_delay -clock $input_clock -min $dv_are                                [get_ports $input_ports];
set_input_delay -clock $input_clock -max [expr $input_clock_period/2 - $dv_bre] [get_ports $input_ports] -clock_fall -add_delay;
set_input_delay -clock $input_clock -min $dv_afe                                [get_ports $input_ports] -clock_fall -add_delay;
 
Failing path are attached as pictures.
 
When i give command report_compile_order –constraints the tcl console shows only one xdc file that is added by me. It's not showing fifo generated xdc files. those xdc file do have set_max_delay and set_false_path constraints but i don't think xilinx is picking them up. Do i have to add them manually?

如果这些路径无法纠正，那么可能是另一种方法，以便满足时间要求？



以下为原文

If these paths can not be corrected what could be another method so that timings are met?

（理想情况下，我们应该看到详细的路径报告，但......）
虽然它们位于FIFO控制器的“时钟交叉”部分，但它们实际上可能不是时钟交叉路径;
它们可能完全是556MHz域的路径。
你没有告诉我们你使用的是什么设备，但是556MHz非常快 - 核心无法以这种速度运行并不奇怪。
您可能需要重新思考自己的工作方式。
由于这是一个时钟跨越FIFO进入较慢的域，你可以将数据宽度加倍，然后以1/2的时钟速率运行FIFO吗？
基本上收集两个样本，然后传输到1/2时钟速率时钟（278MHz），然后使用此时钟作为FIFO的写入时钟。
我不知道556MHz时钟来自哪里，但如果这是一个输入接口，你或许可以直接在ISERDES（反序列化速率加倍）和BUFR（加倍分频器）中完成。
你为什么不给我们更多关于你要做什么的信息......
Avrum



以下为原文

(Ideally we should see the detailed path report, but...)
 
While these are in the "clock crossing" part of the FIFO controller, they are probably not actually clock crossing paths; they are probably paths wholly on the 556MHz domain.
 
You don't tell us what device you are using, but 556MHz is quite fast - its not entirely surprising that the core can't run at this speed.
 
You may need to re-think how you are doing things. Since this is a clock crossing FIFO into a slower domain, can you maybe double the data width and then run the FIFO at 1/2 the clock rate? Basically collect two samples, transfer then to a 1/2 clock rate clock (278MHz), then use this clock as the write clock of your FIFO. I don't know where the 556MHz clock comes from, but if this is an input interface, you might be able to do this directly in the ISERDES (double the deserialization rate) and BUFR (double the divider).
 
Why don't you give us more information on what you are trying to do...
 
Avrum

我在AC701板上玩artix 7。
它的最大bufg频率是628 MHz。
数据通路的宽度加倍并不在我的手中，因为数据来自高速解复用器，它以556 MHz时钟在DDR上发送16位数据。
我使用IDDR在FPGA中获取这些数据。



以下为原文

I am using artix 7 on AC701 board. Its max bufg frequenacy is 628 MHz.
 
doubling width of datapath is not in my hand as data is coming from a high speed demux which is sending 16 bit data on DDR at 556 MHz clock.
 
I am getting this data in FPGA using IDDR.

数据通路的宽度加倍并不在我的手中，因为数据来自高速解复用器，它以556 MHz时钟在DDR上发送16位数据。
为什么不？
采用556MHz输入时钟（可能是在具有时钟功能的I / O上）并将其驱动到BUFIO和BUFR。
将BUFR设置为除以2模式。
捕获ISERDES模块中的所有数据位，解串率为4，并处于DDR模式。
使用BUFIO驱动ISERDES的CLK引脚和BUFR来驱动ISERDES的CLKDIV引脚。
现在，ISERDES的输出在278MHz时为每引脚4位。
获取此数据并使用FIFO将其交叉到150MHz域。
这正是Xilinx在FPGA中具有ISERDES模块的原因;
它允许您在电路板上接收速度非常快的接口，并将它们转换为FPGA内更宽更慢的接口。
Avrum



以下为原文

doubling width of datapath is not in my hand as data is coming from a high speed demux which is sending 16 bit data on DDR at 556 MHz clock.
 
Why not?
 
Take the 556MHz input clock (presumably on a clock capable I/O) and drive it to both a BUFIO and a BUFR.
 
Set the BUFR in divide by 2 mode.
 
Capture all the data bits in ISERDES modules with a deserialization rate of 4 and in DDR mode.
 
Use the BUFIO to drive the CLK pin of the ISERDES and the BUFR to drive the CLKDIV pin of the ISERDES.
 
Now the output of the ISERDES is 4 bits per pin at 278MHz. Take this data and cross it into your 150MHz domain using the FIFO.
 
This is pretty much exactly why Xilinx has the ISERDES modules in the FPGA; it allows you to take in interfaces that are very high speed on the board and convert them to wider and slower interfaces inside the FPGA.
 
Avrum

等等 - 你说你的接口是256位宽，556MHz  - 所以这可能是128位DDR？
首先，这可能是不可能的......
您的接口是使用单端还是差分信令？
如果它是单端的，这是非常快的 - 试图在556MHz下进行单端DDR捕获可能是不可能的，因为它仅在上升沿和下降沿之间仅存在边缘不平衡。
由于捕获的微小窗口（900ps！），在DDR时钟表边缘不平衡可能使这几乎不可能。还有抖动，数据边缘不平衡，信号完整性（特别是符号间干扰），电路板偏斜，封装偏斜，时钟
歪斜....即使使用每位动态校准，这也许是不可能的。
如果您的接口是差分接口，则边缘不平衡消失，时序变得更好。
但是，您只能将24个差分信号放入一个存储区。
只有一个带BUFIO时钟的时钟接口只能跨越3个存储区，这意味着最多可以存储72个信号......
因此，假设这是单端，您可以更好地将时钟放在MRCC引脚上，因为您需要为多个bank的输入提供时钟。
此外，时钟必须位于连接三位128位数据的三个连续存储体中间的两个MRCC引脚之一。
如果您有任何其他引脚排列，此界面无法工作。
由于接口不止一个Bank宽，您需要使用BUFMR。
从IBUF（在MRCC上）直接驱动到BUFMR。
BUFRM输出转发到与MRCC相同的BUFIO和BUFR的输入，以及上面区域中的BUFIO和BUFR以及下面区域中的BUFIO和BUFR。
然后，您需要使用7系列时钟用户指南（UG472）附录A“BUFR对齐”（第110页中的第108页）中所述的BUFR对齐技术。
现在您可以捕获您的数据。
你将在278MHz获得512位。
在时钟交叉缓冲器的远端（150MHz），您可能需要对这些位进行去交错（因为512位实际上是128位输入总线的4个样本，每个第4位属于一个字）。
Avrum



以下为原文

Wait - you said that your interface is 256 bits wide at 556MHz - so presumably this is 128 bits DDR?
 
First of all, this may not be possible...
 
Is your interface using single ended or differential signalling?
 
If it is single ended, this is AWFULLY fast - trying to do single ended DDR capture at 556MHz may well be impossible due he edge imbalance alone between the rising and falling edges alone. Due to the tiny window to capture (900ps!), at DDR the clockk edge imbalance can make this pretty much impossible.There is also jitter, data edge imbalance, signal integrity (particularly inter symbol interference), board skew, package skew, clock skew.... Even with per bit dynamic calibration, this may well be impossible.
 
If your interface is differential, the edge imbalance goes away, and the timing becomes better. However, you can only put 24 differential signals into one bank. An interface with only one clock with BUFIO clocking can only span 3 banks, which means a maximum of 72 signals...
 
So, assuming this is single end, you had BETTER have your clock on an MRCC pin, since you need to clock more than one bank's worth of inputs. Furthermore the clock must be on one of the two MRCC pins in the middle of the three consecutive banks that carry your 128 bits of data. If you have any other pin arrangement, this interface can't work.
 
Since the interface is more than one bank wide, you need to use the BUFMR.
 
From the IBUF (on the MRCC) drive directly to the BUFMR. The BUFRM output goes to the inputs of the BUFIO and BUFR in the same bank as the MRCC as well as the BUFIO and BUFR in the region above and the BUFIO and the BUFR in the region below.
 
Then you need to use the BUFR Alignment technique described in the 7 Series Clocking User Guide (UG472) Appendix A "BUFR Alignment" (p. 108 in v1.10).
 
Now you can capture your data. You will get 512bits at 278MHz. On the far side of your clock crossing buffer (at 150MHz), you will likely need to de-interleave these bits (as the 512 bits really is 4 samples of your 128 bit input bus, with each 4th bit belonging to one word).
 
Avrum

我正在使用IDDR捕获数据。
数据是单比特。
我附加了demux的时序图以及它如何连接到fpga。
你能告诉我如何降低时钟频率吗？



以下为原文

I am using IDDR to capture data. Data is single bit. I am attaching timing diagram of demux and how it is connected to fpga. Can you please tell how to lower clock frequency ?

数据和时钟是差分的。
我正在使用ibufds将它们转换为单端，然后将它们送到IDDR。



以下为原文

data and clock are differential. I am using ibufds to convert them to single ended and then feeding them to IDDR.

因此，在时钟的每个边沿输出8位IDDR的16位数据被移入移位寄存器，以产生256位的块用于进一步处理。
数据处理器的工作频率为150 MHz，因此我使用此CDC FIFO存储写入556 Mhz时钟的256位数据，并以150 MHz读取。
多数民众赞成的故事。



以下为原文

so 16 bit data at output of 8 IDDR on every edge of clock are shifted into a shift register to make a chunk of 256 bits for further processing. the data processor is working at 150 MHz so I am using this CDC FIFO to store 256 bit data written on 556 Mhz clock and read on 150 MHz. Thats whole story.

那么你真的只能在556 MHz的每16个时钟周期写一次FIFO吗？
-  Gabor



以下为原文

So really you only write the FIFO on every 16th clock cycle of 556 MHz?
-- Gabor

那是对的



以下为原文

that's correct

所以，甚至更好。
在8：1反序列化中使用ISERDES（在DDR模式下）。
对于8个数据位中的每一个，这将导致每个周期在139MHz的8位数据（在139MHz时每个时钟总共64位）。
将其中的4个组合在一起得到256位字，并将它们写入FIFO。
这样，只有ISERDES的高速侧运行在556MHz  -  ISERDES的低速侧以及将这些字组合在一起得到256位并将它们写入FIFO的逻辑运行在139MHz。
在这些速度下，FIFO逻辑不会出现任何问题。
高速接口的目标是尽快让它们“缓慢而宽阔”;
具有最少量的逻辑以高时钟速度运行。
Avrum



以下为原文

So, even better.
 
Use the ISERDES in 8:1 deserialization (in DDR mode). This will result in 8 bits of data every cycle at 139MHz for each of your 8 data bits (for a total of 64 bits per clock at 139MHz). Combine 4 of these together to get your 256 bit word and write them to the FIFO.
 
This way, only the high speed side of the ISERDES is running at 556MHz - the low speed side of the ISERDES and the logic to combine the words together to get 256 bits and write them to the FIFO is running at 139MHz. At these speeds you won't have any problems with the FIFO logic.
 
The goal with high speed interfaces is to get them "slow and wide" as soon as possible; have the least amount of logic running at the high clock speed.
 
Avrum

非常感谢您的支持。
非常感激



以下为原文

Thank you very much for your support. Much appreciated