FPGA中的IIR滤波器很难实现时钟周期延迟

在上面的等式中，输入u（k）并且输出y（k）滤波器。



以下为原文

In the above Equation u(k) is input and y(k) is output of the filter.

嗨，
DSP48切片将有可选的寄存器，可能你已启用它们，请检查。
另外请参考beloe relavant链接获取更多视图，该概念与家庭无关，但数字可能略有不同，您可以从各自的设备DSP48 UG获得
http://forums.xilinx.com/t5/Virtex-Family-FPGAs/DSP48-slices-what-is-their-latency/td-p/228591
希望这可以帮助。
问候，
Vanitha。
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以下为原文

Hi,
 
DSP48 slices will have optional registers , may be you have enabled them, please check.
 
Also do refer beloe relavant link for more views, the concept remains same irrespective of family but the figures may vary slightly which you can get from respective device DSP48 UG
 
http://forums.xilinx.com/t5/Virtex-Family-FPGAs/DSP48-slices-what-is-their-latency/td-p/228591
 
 
Hope this helps.
 
Regards,
Vanitha.
---------------------------------------------------------------------------------------------
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Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented

嗨，
如果您想了解现有的IIR解决方案，请参阅以下链接
http://www.cs.york.ac.uk/rts/docs/Xilinx-datasource-2003-q1/whitepapers/wp116.pdf
http://www.xilinx.com/support/documentation/white_papers/wp330.pdf
http://forums.xilinx.com/t5/DSP-Tools/IIR-filter-design-in-System-Generator/td-p/191162
希望这可以帮助。
问候，
Vanitha。
--------------------------------------------------
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您可能会找到相关信息。请留下帖子 - “接受为解决方案”，如果提供的信息有用且回复，请给予赞誉



以下为原文

Hi,
 
In case you wanated to know about existing IIR solutions , please refer below links as well
 
http://www.cs.york.ac.uk/rts/docs/Xilinx-datasource-2003-q1/whitepapers/wp116.pdf
 
http://www.xilinx.com/support/documentation/white_papers/wp330.pdf
 
http://forums.xilinx.com/t5/DSP-Tools/IIR-filter-design-in-System-Generator/td-p/191162
 
Hope this helps.
 
Regards,
Vanitha.
---------------------------------------------------------------------------------------------
Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented