如何在CY7C68013A-128AXC中配置slave fifo接口

嗨，伙计们，最近，我正在开发一个USB项目，其中CY7C68013A-128AXC被用来通过奴隶FIFO接口与FPGA通信，在68013中，EP2被配置为512字节双缓冲Mulnual OFF FIFO，EP6被配置为FIFO中的512字节双缓冲自动，IFCK来自外部的。在痛苦的调试，我看到在Slave FIFO接口很奇怪的行为：当FPGA读取数据从68013到从属FIFO接口，我们必须设置慢点fifopinpolar登记为“1”，之后，FPGA可以正确地从Slave FIFO接口无论什么价值出现读取数据S在SLLE PIN，即使驱动器0’上的SLLE引脚。否则，如果我们把莓点fifopinpolar登记为“0”，那么我们永远无法读取数据从Slave FIFO甚至我们开车慢销到“0”，在Slave FIFO数据总线就像HIGHZ状态。当FPGA数据写入68013，情况是相反的从68013读取数据。我们必须把莓点fifopinpolar登记为“零”，之后，FPGA可以正确写数据到68013不管通过什么价值Slave FIFO接口出现在慢销，即使驱动器“0”慢销。否则，如果我们把莓点fifopinpolar登记为“1”，然后我们可以不写数据到68013通过从属FIFO接口，甚至我们开车慢销0。我相信慢销连接是好的，它不是浮。以下是td_init() 68013固件，有任何错误的配置？td_init？虚空（void）//调用一次启动{ //设置CPU的时钟48mhz cpucs =（（cpucs &；~ bmclkspd）| bmclkspd1）；revctl = 0x03；//必须设置revctl。0和revctl。1到1 syncdelay；/ / fiforeset = 0x80；/ /激活nak-all避免竞争条件syncdelay；/ / fiforeset = 0x02；/ /复位FIFO 2 syncdelay；fiforeset = 0x06；/ /复位FIFO 6 syncdelay；/ / / / / /关闭fiforeset = 0x00；nak-all syncdelay；//设置从属FIFO接口48mhz，使用外部时钟ifconfig = 0x43；syncdelay；ep2fifocfg = 0x01；/ /手了syncdelay；ep2cfg = 0xa2；syncd时滞；ep6fifocfg = 0x09；/ / autoin syncdelay；ep6cfg = 0xe2；SYNCDELAY；/ /！！！！！！！！当外部FIFO读硕士的数据从接口，在登记fifopinpolar莓位必须设置为1，fifopinpolar = 0x10 / /！！！！！！！！当外部FIFO主数据写入从站接口，在登记fifopinpolar莓位必须设置为0，fifopinpolar = 0x00 fifopinpolar = 0x00；syncdelay；ep6autoinlenh = 0x02；/你可以定义这些如你所愿，syncdelay；/有FX2自动限制的ep6autoinlENL = 0x00；syncdelay；syncdelay；ep2bcl = 0x80；/ /手臂ep2out写字节数W /跳过。syncdelay；ep2bcl = 0x80；SYNCDELAY；//使双autopointer特征autoptrsetup | = 0x01；rwuen = true；/ /启用远程唤醒}



     以下为原文
          hi guys,   
   
recently, I'm developing a u*** project, in which Cy7c68013A-128AXC is used to communicate with FPGA through slave fifo interface,   
in the 68013, EP2 is configured as 512 bytes double buffered mannual out fifo, EP6 is configured as 512 byte double buffered auto-in fifo, IFCLK is coming from external.   
   
after painful debugging, I saw very strange behavior in the slave fifo interface:   
   
when FPGA read data from 68013 through slave fifo interface, we must set the SLOE bit of FIFOPINPOLAR register to be '1', after that, FPGA can correctly read data from slave fifo interface no matter what value appears in SLOE pin, even though drive '0' on SLOE pin.   
otherwise, if we set the SLOE bit of FIFOPINPOLAR register to be '0', then we can never read data out from slave fifo even we drive SLOE pin to '0', the data bus on slave fifo looks like in HighZ state.   
   
when FPGA write data into 68013, the condition is contrary to read data from 68013. we must set the SLOE bit of FIFOPINPOLAR register to be '0', after that, FPGA can correctly write data into 68013 through slave fifo interface no matter what value appears in SLOE pin, even though drive '0' on SLOE pin.   
otherwise, if we set the SLOE bit of FIFOPINPOLAR register to be '1', then we can never write data into 68013 through slave fifo interface, even we drive SLOE pin to '0'.   
   
and I'm sure that the SLOE pin connection is ok, it's not floating.   
   
following is TD_init() in 68013 firmware, is there any wrong configuration??   
   
void TD_Init(void) // Called once at startup   
{   
// set the CPU clock to 48MHz   
CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1) ;   
   
REVCTL = 0x03; // MUST set REVCTL.0 and REVCTL.1 to 1   
SYNCDELAY; //   
FIFORESET = 0x80; // activate NAK-ALL to avoid race conditions   
SYNCDELAY; //   
FIFORESET = 0x02; // reset, FIFO 2   
SYNCDELAY;   
FIFORESET = 0x06; // reset, FIFO 6   
SYNCDELAY; // //   
FIFORESET = 0x00; // deactivate NAK-ALL   
SYNCDELAY;   
   
// set the slave FIFO interface to 48MHz, use external clock   
IFCONFIG = 0x43;   
SYNCDELAY;   
   
EP2FIFOCFG = 0x01; // mannual out   
SYNCDELAY;   
EP2CFG = 0xA2;   
SYNCDELAY;   
EP6FIFOCFG = 0x09; // autoin   
SYNCDELAY;   
EP6CFG = 0xE2;   
SYNCDELAY;   
   
// !!!!!! when external fifo master read data from slave interface, the SLOE bit in register FIFOPINPOLAR must set to be 1, FIFOPINPOLAR = 0x10   
// !!!!!! when external fifo master write data into slave interface, the SLOE bit in register FIFOPINPOLAR must set to be 0, FIFOPINPOLAR = 0x00   
FIFOPINPOLAR = 0x00;   
SYNCDELAY;   
   
EP6AUTOINLENH = 0x02; // you can define these as you wish,   
SYNCDELAY; // to have the FX2 automatically limit IN's   
EP6AUTOINLENL = 0x00;   
SYNCDELAY;   
   
   
SYNCDELAY;   
EP2BCL = 0x80; // ARM EP2OUT by writing byte count w/skip.   
SYNCDELAY;   
EP2BCL = 0x80;   
SYNCDELAY;   
   
// enable dual autopointer feature   
AUTOPTRSETUP |= 0x01;   
   
Rwuen = TRUE; // Enable remote-wakeup   
}