不能从FIFO引脚获得输出数据

在TRM的第32页中显示12个可能的端点配置。你在跟踪这个吗？



     以下为原文
          In page 32 of the trm the 12 possible endpoint configurations is displayed. Are you following this?   

对。当EP8被输出时，我们已经使用了第十一个融合（EP2 1024×3，EP8×512×2）。和第一配置（EP2 512×2，EP8 512×2），当输出EP2时。



     以下为原文
          Yes. We have used the 11th conifguration (ep2 1024 x 3, ep8 512 x 2), when ep8 was output. And the first configuration (ep2 512 x 2, ep8 512 x 2), when ep2 was output.   

我来看看我能不能测试一下你所描述的…我记得EP8工作得很好…



     以下为原文
          I'll see if i can test what you are describing... i remember ep8 working fine...   

这里是TDY-IIT函数：CPUCS=（（CPUCS&，~BMCLKSPD），BMCLKSPD1）；SYNCDELAY；/ /将CPU时钟设置为48 MHz的同步延迟；IFCONFIG＝0x03；SYNCDELAY；// 0 0 0 0 0 0 1 1 / /π/ /μi /从从FIFO接口/ /μi端口E无GSTAT/ /或从属FIFO的操作。同步/ /πiFLK在三态/ /内时钟（1）/IFCK ReVCTL＝0x03的外/时钟源上没有反转/ / /πiFLK；SimcRead；SYNCDELAY；//CyPress高度推荐将这两位设置为“1”。s EP2CFG＝0xEB；SYNCDELAY；// 1，1，0，1，0，1，1／/μ。三/ / /ε-保留/ /或γ/ 1024 / /体积/ / /有效/ EP8CFG＝0xA2；SYNCDELAY；// 1 0 0 0 0 0 0 / 1 0 / /π/ /π/ /π/ /π/ / 512 / / 512 / / 512 / / /散布/ /或有效的EP4CFG＝0；γ/ /β＝0；SycCelp；EP1OutCFG= BMPIT5；SYNCDELAY；//无效，批量EP1CIFFG＝BMPIT5；SYNCDELAY；//Value/Bult//NAK全部并重置端点FiPosie= 0x80；SimcRead；FiPosie= 0x02；SimcRead；FiPosie= 0x08；SimcRead；FiPosie= 0x00；SYNCDELAY；//恢复正常操作OUTpkTale= 0x88；SycCdTray= 0x88；SycCdEnter；EP2FIFOFFG＝0x0d；SYNCDELAY；// 0 0 0 0 1 1 0 / 1 / /μ/ /π/ /π16位/ /μz Z-LeN发送允许/ /或γi Autin（仅适用于端点）/ /没有自动输出（仅适用于输出端点）//OEP（仅适用于出端点）/通知（仅适用于在端点）ep8fifocfg = 0x11；SYNCDELAY；/ / 0 0 0 1 0 0 0 1 / / | | | | | | / | | | | | 16bit／／| | | | z-len发送不允许/ | | |没有autoin（适用只有在端点）/ | | autoout（仅适用于出端点）/ | OEP（适用于LY出端点）/通知（仅适用于在端点）ep4fifocfg = 0；syncdelay；ep6fifocfg = 0；syncdelay；ep2autoinlenh = 0x04；SYNCDELAY；/ / 1024 ep2autoinlenl = 0x00；SYNCDELAY；//因为默认双缓冲必须写虚拟字节数的两倍syncdelay；ep8bcl = 0X80；//ARM EP8OUT通过写入字节计数W/SKIP。syncdelay；ep8bcl = 0x80；syncdelay；ep0bch = 0；syncdelay；ep0bcl = 0；syncdelay；fifopinpolar = 0x00；SYNCDELAY；/ / 0 0 0 0 0 0 0 0 / / | | | | | | | | / | | | | | | |满标志极性（低电平）/ / | | | | | |空旗极性（低电平）/ | | | | | SLWR极性（主动低）/ | | | | SLRD极性（低电平）/ | | |野李极性（低电平）/ | | pktend极性（低电平）/不使用pinflagsab = 0xbc；SYNCDELAY；/ / 1 0 1 1 1 1 0 0 / / | | | | | | | | / | | | |国旗表明EP2全/ / B旗表明EP8空portacfg = 0；syncdelay；/0 / 0 0 0 0 0 0 0 / / | | | | | | | | / | | | | | | | PA0不是INT0 / | | | | | | PA1不是INT1 / | |不习惯/ | SLC /不flagd PA7



     以下为原文
          Here is TD_Init function:   
   
CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1); SYNCDELAY; // set the CPU clock to 48MHz   
   
SYNCDELAY;   
   
IFCONFIG = 0x03; SYNCDELAY;   
// 0 0 0 0 0 0 1 1   
// | | | | | | | |   
// | | | | | | slave fifo interface   
// | | | | | port e no gstate   
// | | | | slave fifo's operate synchrously   
// | | | IFCLK is not inverted   
// | | IFCLK in tri-state   
// | internal clockis 48Mhz (not used)   
// external clock source on IFCLK   
   
REVCTL = 0x03; SYNCDELAY;SYNCDELAY;//Cypress highly recommends setting both bits to '1'.s   
   
EP2CFG = 0xEB; SYNCDELAY;   
// 1 1 1 0 1 0 1 1   
// | | | | | | | |   
// | | | | | | triple   
// | | | | | reserved   
// | | | | 1024   
// | | bulk   
// | in   
// valid   
   
EP8CFG = 0xA2; SYNCDELAY;   
// 1 0 1 0 0 0 1 0   
// | | | | | | | |   
// | | | | | | double   
// | | | | | reserved   
// | | | | 512   
// | | bulk   
// | out   
// valid   
   
EP4CFG = 0; SYNCDELAY;   
EP6CFG = 0; SYNCDELAY;   
   
EP1OUTCFG = bmBIT5; SYNCDELAY; //Invalid, bulk   
EP1INCFG = bmBIT5; SYNCDELAY; //Invalid, bulk   
   
//Nak all and reset the endpoints   
FIFORESET = 0x80; SYNCDELAY;   
FIFORESET = 0x02; SYNCDELAY;   
FIFORESET = 0x08; SYNCDELAY;   
FIFORESET = 0x00; SYNCDELAY; //Restore normal operation   
   
OUTPKTEND = 0x88;SYNCDELAY;   
OUTPKTEND = 0x88;SYNCDELAY;   
   
EP2FIFOCFG = 0x0D; SYNCDELAY;   
// 0 0 0 0 1 1 0 1   
// | | | | | |   
// | | | | | 16bit   
// | | | | z-len send allowed   
// | | | autoIN (applies only to IN endpoints)   
// | | no autoOUT (applies only to OUT endpoints)   
// | OEP (applies only to OUT endpoints)   
// INFM (applies only to IN endpoints)   
   
EP8FIFOCFG = 0x11; SYNCDELAY;   
// 0 0 0 1 0 0 0 1   
// | | | | | |   
// | | | | | 16bit   
// | | | | z-len send not allowed   
// | | | no autoIN (applies only to IN endpoints)   
// | | autoOUT (applies only to OUT endpoints)   
// | OEP (applies only to OUT endpoints)   
// INFM (applies only to IN endpoints)   
   
EP4FIFOCFG = 0; SYNCDELAY;   
EP6FIFOCFG = 0; SYNCDELAY;   
   
EP2AUTOINLENH = 0x04; SYNCDELAY; //1024   
EP2AUTOINLENL = 0x00; SYNCDELAY;   
   
// since the defaults are double buffered we must write dummy byte counts twice   
SYNCDELAY;   
EP8BCL = 0x80; // arm EP8OUT by writing byte count w/skip.   
SYNCDELAY;   
EP8BCL = 0x80;   
   
SYNCDELAY;   
EP0BCH = 0;   
SYNCDELAY;   
EP0BCL = 0;   
SYNCDELAY;   
   
FIFOPINPOLAR = 0x00; SYNCDELAY;   
// 0 0 0 0 0 0 0 0   
// | | | | | | | |   
// | | | | | | | full flag polarity (active low)   
// | | | | | | empty flag polarity (active low)   
// | | | | | slwr polarity (active low)   
// | | | | slrd polarity (active low)   
// | | | sloe polarity (active low)   
// | | pktend polarity (active low)   
// not used   
   
PINFLAGSAB = 0xBC;SYNCDELAY;   
// 1 0 1 1 1 1 0 0   
// | | | | | | | |   
// | | | | flag A indicates ep2 full   
// flag B indicates ep8 empty   
   
PORTACFG = 0;SYNCDELAY;   
// 0 0 0 0 0 0 0 0   
// | | | | | | | |   
// | | | | | | | PA0 - not int0   
// | | | | | | PA1 - not int1   
// | | not used   
// | SLCS   
// PA7 - not FlagD