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我收到错误XST:528多源信号单元>; 此信号连接到多个驱动程序。 我无法理解为什么我会收到此错误。 我尝试了很多... 任何人都可以帮我清理那个。 port(rst:in std_logic; clk:in std_logic; status:in std_logic_vector(27 downto 0); slatch:in std_logic; PERIOD0:inout std_logic_vector(31 downto 0); PERIOD1:inout std_logic_vector(31 downto 0); PERIOD2:inout std_logic_vector(31 downto 0); PERIOD3:inout std_logic_vector(31 downto 0); PERIOD4:inout std_logic_vector(31 downto 0); PERIOD5:inout std_logic_vector(31 downto 0); PERIOD6:inout std_logic_vector(31 downto 0); PERIOD7:inout std_logic_vector(31 downto 0); PERIOD8:inout std_logic_vector(31 downto 0); PERIOD9:inout std_logic_vector(31 downto 0); PERIOD10:inout std_logic_vector(31 downto 0); PERIOD11:inout std_logic_vector(31 downto 0); PERIOD12:inout std_logic_vector(31 downto 0); PERIOD13:inout std_logic_vector(31 downto 0); PERIOD14:inout std_logic_vector(31 downto 0); PERIOD15:inout std_logic_vector(31 downto 0); PERIOD16:inout std_logic_vector(31 downto 0); PERIOD17:inout std_logic_vector(31 downto 0); PERIOD18:inout std_logic_vector(31 downto 0); PERIOD19:inout std_logic_vector(31 downto 0); PERIOD20:inout std_logic_vector(31 downto 0); PERIOD21:inout std_logic_vector(31 downto 0); PERIOD22:inout std_logic_vector(31 downto 0); PERIOD23:inout std_logic_vector(31 downto 0); PERIOD24:inout std_logic_vector(31 downto 0); PERIOD25:inout std_logic_vector(31 downto 0); PERIOD26:inout std_logic_vector(31 downto 0); PERIOD27:inout std_logic_vector(31 downto 0); P0:out std_logic_vector(31 downto 0); P1:输出std_logic_vector(31 downto 0); P2:输出std_logic_vector(31 downto 0) );结束基础; 建筑行为的根本是 type cbus是std_logic_vector的数组(0到27)(31 downto 0); 信号cb:cbus; type minimum是std_logic_vector的数组(0到6)(31 downto 0); 信号最小值:最小值; 信号tmp:最小; type selp是std_logic_vector的数组(0到2)(31 downto 0); 信号minp:selp; signal pc:std_logic:='0'; 信号i:整数范围0到3:= 0; 信号j,k:整数范围0到6:= 0; 开始 min(0)min(1)min(2)min(3)min(4)min(5)min(6)tmp(0)tmp(1)tmp(2)tmp(3)tmp(4)tmp( 5)tmp(6)minp(0)minp(1)minp(2)过程(clk)开始if(clk'event和clk ='1'和slatch ='1')thencb(0)cb(1)cb (2)CB(3)CB(4)CB(5)CB(6)CB(7)CB(8)CB(9)CB(10)CB(11)CB(12)CB(13)CB(14 )CB(15)CB(16)CB(17)CB(18)CB(19)CB(20)CB(21)CB(22)CB(23)CB(24)CB(25)CB(26)CB (27)结束if; end process; 过程(clk,slatch)开始if(rst ='1')thenpc min(0)min(1)min(2)min(3)min(4)min(5)min(6)“00000000000000000000000000000000”和tmp( k)minp(j)结束if; if(j = 6)thentmp(j)结束if; end loop; 结束循环;结束if;结束过程; P0P1P2end行为; 以上来自于谷歌翻译 以下为原文 Hello all I 'am getting the error XST:528 Multi-source in Unit Can anyone help me in clearing that.? port ( rst : in std_logic; clk : in std_logic; status : in std_logic_vector(27 downto 0); slatch : in std_logic; PERIOD0 : inout std_logic_vector(31 downto 0); PERIOD1 : inout std_logic_vector(31 downto 0); PERIOD2 : inout std_logic_vector(31 downto 0); PERIOD3 : inout std_logic_vector(31 downto 0); PERIOD4 : inout std_logic_vector(31 downto 0); PERIOD5 : inout std_logic_vector(31 downto 0); PERIOD6 : inout std_logic_vector(31 downto 0); PERIOD7 : inout std_logic_vector(31 downto 0); PERIOD8 : inout std_logic_vector(31 downto 0); PERIOD9 : inout std_logic_vector(31 downto 0); PERIOD10 : inout std_logic_vector(31 downto 0); PERIOD11 : inout std_logic_vector(31 downto 0); PERIOD12 : inout std_logic_vector(31 downto 0); PERIOD13 : inout std_logic_vector(31 downto 0); PERIOD14 : inout std_logic_vector(31 downto 0); PERIOD15 : inout std_logic_vector(31 downto 0); PERIOD16 : inout std_logic_vector(31 downto 0); PERIOD17 : inout std_logic_vector(31 downto 0); PERIOD18 : inout std_logic_vector(31 downto 0); PERIOD19 : inout std_logic_vector(31 downto 0); PERIOD20 : inout std_logic_vector(31 downto 0); PERIOD21 : inout std_logic_vector(31 downto 0); PERIOD22 : inout std_logic_vector(31 downto 0); PERIOD23 : inout std_logic_vector(31 downto 0); PERIOD24 : inout std_logic_vector(31 downto 0); PERIOD25 : inout std_logic_vector(31 downto 0); PERIOD26 : inout std_logic_vector(31 downto 0); PERIOD27 : inout std_logic_vector(31 downto 0); P0 : out std_logic_vector(31 downto 0); P1 : out std_logic_vector(31 downto 0); P2 : out std_logic_vector(31 downto 0) ); end fundamental; architecture Behavioral of fundamental is type cbus is array (0 to 27) of std_logic_vector(31 downto 0); signal cb : cbus ; type minimum is array (0 to 6) of std_logic_vector(31 downto 0); signal min: minimum; signal tmp: minimum; type selp is array (0 to 2) of std_logic_vector(31 downto 0); signal minp: selp; signal pc : std_logic:='0'; signal i: integer range 0 to 3:=0; signal j,k: integer range 0 to 6:=0; begin min(0) <= "11111111111111111111111111111111"; min(1) <= "11111111111111111111111111111111"; min(2) <= "11111111111111111111111111111111"; min(3) <= "11111111111111111111111111111111"; min(4) <= "11111111111111111111111111111111"; min(5) <= "11111111111111111111111111111111"; min(6) <= "11111111111111111111111111111111"; tmp(0) <= "11111111111111111111111111111111"; tmp(1) <= "11111111111111111111111111111111"; tmp(2) <= "11111111111111111111111111111111"; tmp(3) <= "11111111111111111111111111111111"; tmp(4) <= "11111111111111111111111111111111"; tmp(5) <= "11111111111111111111111111111111"; tmp(6) <= "11111111111111111111111111111111"; minp(0) <= "11111111111111111111111111111111"; minp(1) <= "11111111111111111111111111111111"; minp(2) <= "11111111111111111111111111111111"; process(clk) begin if(clk'event and clk='1' and slatch='1' ) then cb(0)<=PERIOD0; cb(1)<=PERIOD1; cb(2)<=PERIOD2; cb(3)<=PERIOD3; cb(4)<=PERIOD4; cb(5)<=PERIOD5; cb(6)<=PERIOD6; cb(7)<=PERIOD7; cb(8)<=PERIOD8; cb(9)<=PERIOD9; cb(10)<=PERIOD10; cb(11)<=PERIOD11; cb(12)<=PERIOD12; cb(13)<=PERIOD13; cb(14)<=PERIOD14; cb(15)<=PERIOD15; cb(16)<=PERIOD16; cb(17)<=PERIOD17; cb(18)<=PERIOD18; cb(19)<=PERIOD19; cb(20)<=PERIOD20; cb(21)<=PERIOD21; cb(22)<=PERIOD22; cb(23)<=PERIOD23; cb(24)<=PERIOD24; cb(25)<=PERIOD25; cb(26)<=PERIOD26; cb(27)<=PERIOD27; end if; end process; Process(clk, slatch) begin if(rst='1') then pc<='0'; min(0)<="11111111111111111111111111111111"; min(1)<="11111111111111111111111111111111"; min(2)<="11111111111111111111111111111111"; min(3)<="11111111111111111111111111111111"; min(4)<="11111111111111111111111111111111"; min(5)<="11111111111111111111111111111111"; min(6)<="11111111111111111111111111111111"; tmp(0)<="11111111111111111111111111111111"; tmp(1)<="11111111111111111111111111111111"; tmp(2)<="11111111111111111111111111111111"; tmp(3)<="11111111111111111111111111111111"; tmp(4)<="11111111111111111111111111111111"; tmp(5)<="11111111111111111111111111111111"; tmp(6)<="11111111111111111111111111111111"; elsif(clk'event and clk='1' and slatch ='1') then if (status(0)='1') then min(0) <= cb(0); tmp(0)<= cb(0); end if; for i in 1 to 2 loop if (status(i) = '1') then if (cb(i) < min(1)) then min(1) <= cb(i); tmp(1) <= cb(i); end if; end if; end loop; for i in 3 to 5 loop if (status(i) = '1') then if (cb(i) < min(2)) then min(2) <= cb(i); tmp(2) <= cb(i); end if; end if; end loop; for i in 6 to 9 loop if (status(i) = '1') then if (cb(i) < min(3)) then min(3) <= cb(i); tmp(3) <= cb(i); end if; end if; end loop; for i in 10 to 14 loop if (status(i) = '1') then if (cb(i) < min(4)) then min(4) <= cb(i); tmp(4) <= cb(i); end if; end if; end loop; for i in 15 to 20 loop if (status(i) = '1') then if (cb(i) < min(5)) then min(5) <= cb(i); tmp(5) <= cb(i); end if; end if; end loop; for i in 21 to 27 loop if (status(i) = '1') then if (cb(i) < min(6)) then min(6) <= cb(i); tmp(6) <= cb(i); end if; end if; end loop; if(i=27) then pc<='1'; end if; end if; end process; process(clk) ---find out three minimum numbers from tmp arry which is equal to min array, begin if(clk'event and clk='1' and pc='1') then for j in 0 to 2 loop for k in 0 to 6 loop if(tmp(k)>"00000000000000000000000000000000" and tmp(k) < minp(j)) then minp(j)<=tmp(j); end if; if(j=6) then tmp(j)<="00000000000000000000000000000000"; end if; end loop; end loop; end if; end process; P0<=minp(0); P1<=minp(1); P2<=minp(2); end behavioral; |
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7个回答
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我认为你并没有真正检查自己的代码。
当你专注于另一个问题时很容易做到,我同意。 Pout被定义为std_logic_vector(2 downto 0)。 minp定义为std_logic_vector(31 downto 0)的数组(0到2)。 当两者完全不同时,你怎么可能将两者联系在一起? ----------“我们必须学会做的事情,我们从实践中学习。” - 亚里士多德 在原帖中查看解决方案 以上来自于谷歌翻译 以下为原文 I think you are not really checking your own code. Easy to do when you are focussed on another problem, I agree. Pout is defined as a std_logic_vector(2 downto 0). minp is defined as an array (0 to 2) of std_logic_vector(31 downto 0). How could you possibly connect the two together when they are utterly different? ---------- "That which we must learn to do, we learn by doing." - AristotleView solution in original post |
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是因为你在两个不同的地方为minp分配了一个值吗?
它具有连续分配(靠近架构的顶部),并在附加代码底部的(未命名)过程中分配。 我相信如果您阅读完整的综合报告,它会告诉您哪些信号正在驱动多源信号。 问候, 霍华德 ----------“我们必须学会做的事情,我们从实践中学习。” - 亚里士多德 以上来自于谷歌翻译 以下为原文 Is it because you assign a value to minp in two different places? It has a continuous assignment (near the top of your architecture) and it is assigned in the (unnamed) process at the bottom of your attached code. I believe if you read the full synthesis report it will tell you which signals are driving the multisource signal. Regards, Howard ---------- "That which we must learn to do, we learn by doing." - Aristotle |
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1.问题在于你的连续作业不是初始化(这是一个非常“软件”的概念)。
如果要初始化寄存器,则应遵循VHDL实践进行初始化,例如: signal minp:selp:=(others =>(others =>'1')); 这会将数组中的所有元素初始化为“1”(这是您似乎想要做的)。 请注意,这与寄存器的RESET不同,您应该使用一个进程,例如 sync_reset_example:process(clk) 开始 如果rising_edge(clk)那么 if(reset ='1')然后 minp(其他=>'1')); 。 。 。 如果您希望INITIALISE和RESET寄存器,如果两个值相同,那么对这些工具最有帮助,即初始化并重置为全部。 如果不是,你会收到警告。 你提供的例子不是一个过程。 有关流程中的分配,请参阅上面的示例。 ----------“我们必须学会做的事情,我们从实践中学习。” - 亚里士多德 以上来自于谷歌翻译 以下为原文 1. The issue is that your continuous assignments are NOT initialisations (what a very "software" concept that idea is). If you want to initialise the registers, you should follow the VHDL practice for initialisation, e.g. signal minp : selp := (others => (others => '1')); which will initialise ALL elements in the array to '1' (which is what you seem to want to do). Further note that this is not the same thing as a RESET of the register, for which you should use a process, e.g. sync_reset_example : process (clk) begin if rising_edge(clk) then if (reset = '1') then minp <= (others => (others => '1')); . . . If you wish to both INITIALISE and RESET a register it is most helpful to the tools if the two values are the same, i.e. you initialise and reset to all ones. You will get a warning if they are not. 2. The example you have provided IS NOT A PROCESS. See the above example for assignments in a process. ---------- "That which we must learn to do, we learn by doing." - Aristotle |
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您要在两个不同的位置为MinP分配值。
第一个位置是对所有位置的连续分配 minp(0)) 第二个是在最后一个过程中 minp(j))。 这会为同一信号生成两个驱动源,这就是您收到错误的原因。 您必须仅在一个位置为信号指定值。 正如hgleamon1早先评论过的那样,你使用的是一种非常以软件为中心的编码风格,这对硬件设计不起作用。 ------您是否尝试在Google中输入问题? 如果没有,你应该在发布之前。太多结果? 尝试添加网站:www.xilinx.com 以上来自于谷歌翻译 以下为原文 You are assigning values to MinP in two different locations. The first location is the continuous assignment to all ones minp(0) <= "11111111111111111111111111111111";) and the second is in the last process minp(j)<=tmp(j);) . This generates two driver sources for the same signal which is why you are getting the error. You must assign values to a signal in only one place. As hgleamon1 commented earlier you are using a very software centric coding style and this does not work for hardware design. ------Have you tried typing your question into Google? If not you should before posting. Too many results? Try adding site:www.xilinx.com |
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如果它困扰你的想法,还有其他选择吗?
以上来自于谷歌翻译 以下为原文 Is there any alternative to if it stuck your mind.? |
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我不太清楚如何更清楚地解释它。
我会再试一次。 1.请勿对信号minp使用连续分配和过程驱动分配。 2.如果您希望初始化信号,请使用我在本主题的消息4中演示的VHDL合法初始化。 3.如果要复位信号,请在进程内使用同步或异步复位,并使用与初始化时相同的复位值。 这个可以吗? ----------“我们必须学会做的事情,我们从实践中学习。” - 亚里士多德 以上来自于谷歌翻译 以下为原文 I'm not quite sure how to have explained it any clearer. I shall try again. 1. DON'T use both continuous assignments and a process-driven assignment for the signal minp. 2. If you wish to initialise the signal, use the VHDL legal initialisation that I demonstrated in message 4 of this thread. 3. If you wish to reset the signal, use either a synchronous or asynchronous reset inside a process and use the same value for reset as you do for initialisation. Is this OK? ---------- "That which we must learn to do, we learn by doing." - Aristotle |
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这就是我的想法,我该怎么做。
我理解你的回复。 它足够了。 也许我无法纠正这一点。 问候 以上来自于谷歌翻译 以下为原文 thats wthat I'am thinking, How can Ido that.? I understood your reply. its sufficient. perhaps I 'am unable to rectify this. regards |
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