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淘帖
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查看你的.syr文件并检查所有警告 - 你会看到类似的东西
分析库中的模块。警告：Xst：2725 - “receive.v”第56行：案例项和案例选择器之间的大小不匹配。警告：Xst：2725 - “receive.v”第57行：案例项和案例选择器之间的大小不匹配
。
警告：Xst：653 - 信号>已使用但从未分配。
此无源信号将自动连接到值00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000。
警告：Xst：653 - 使用信号但从未分配信号。
此无源信号将自动连接到值0。
您应该使用更现代的命名端口格式来实例化模块：而不是
SPI SPI_0（ReadWriteNot，clk，ADCdin，ADCdout，data，nextstate，ReadStart，DataRead，WriteDone，ReadDone，8,24，CS，Ready，Reset，ADCcsn）;使用：
SPI SPI_0 .ReadWriteNot（ReadWriteNot）,. clk（clk）,. SPIwriteOutput（ADCdin）,. SPIreadInput（ADCdout）,. DataWrite（data）,. WriteStart（nextstate）,. ReadStart（ReadStart）,. DataRead（DataRead），
.WriteDone（WriteDone）,. ReadDone（ReadDone）,. WRriteLength（8），。ReadLength（24）,. CS（CS），。Read（Ready）,. Reset（Reset）,. SPIsync（ADCcsn））;
通常，不要使用非阻塞分配组合逻辑：
总是@（clk）开始ADCsclk = 4）开始channelstate end end default：数据endcase end始终@（posedge clk）begin if if（ReceivingData == 1）begin if if（ReadDone == 1）begin if if（state == 6）begin
case（channelstate）8'h00：AnalogIData0 [23：0] 8'h01：AnalogIData1 [23：0] 8'h02：AnalogIData2 [23：0] 8'h03：AnalogIData3 [23：0] 8'h04：AnalogIData4 [
23：0]默认值：temp endcase end end end endalways @（clk）begin ADCsclk 以下为原文
You have some other issues as well.
Look at your .syr file and examine all the warnings - you'll see stuff like
Analyzing module
WARNING:Xst:2725 - "receive.v" line 56: Size mismatch between case item and case selector.
WARNING:Xst:2725 - "receive.v" line 57: Size mismatch between case item and case selector.
WARNING:Xst:653 - Signal
WARNING:Xst:653 - Signal
You should instantiate modules using the more modern named port format: Instead of
SPI SPI_0(ReadWriteNot,clk, ADCdin, ADCdout, data, nextstate, ReadStart, DataRead, WriteDone, ReadDone,8, 24, CS, Ready, Reset,ADCcsn);
use:
SPI SPI_0
.ReadWriteNot (ReadWriteNot),
.clk (clk),
.SPIwriteOutput (ADCdin),
.SPIreadInput (ADCdout),
.DataWrite (data),
.WriteStart (nextstate),
.ReadStart (ReadStart),
.DataRead (DataRead),
.WriteDone (WriteDone),
.ReadDone (ReadDone),
.WriteLength (8),
.ReadLength (24),
.CS (CS),
.Ready (Ready),
.Reset (Reset),
.SPIsync (ADCcsn)
);
In general, don't use non-blocking assignments incombinatorial logic:
always@(clk)
begin
ADCsclk <= clk; // !!!! should be =
end
Below are other comments for your original code. See the !!!! comments.
`timescale 1ns / 1ps
module ADC(clk,
AnalogIData0,
AnalogIData1,
AnalogIData2,
AnalogIData3,
AnalogIData4,
ADCsclk,
ADCdout,
ADCrdyn,
ADCresetn,
ADCcsn,
ADCdin
);
input clk;
output reg [23:0] AnalogIData0;
output reg [23:0] AnalogIData1 ;
output reg [23:0] AnalogIData2 ;
output reg [23:0] AnalogIData3 ;
output reg [23:0] AnalogIData4;
output reg ADCsclk= 1'b0;
input ADCdout;
input ADCrdyn;
output reg ADCresetn = 1'b1;
output wire ADCcsn;
output wire ADCdin;
reg ReadWriteNot = 1'b0;
wire clk;
wire [31:0] DataWrite;
wire WriteStart;
reg ReadStart = 1'b0;
wire [31:0] DataRead;
wire ReadDone;
wire WriteDone;
wire CS;
wire Reset;
wire Ready;
reg ReceivingData = 1'b0;
reg [7:0] state = 8'h00;
reg nextstate = 1'b0;
reg [7:0] channelstate = 1'b0; // !!!! use 'b0 or 8'b0
reg [31:0] data = 32'h00000000;
reg [31:0] count = 1'b0; // !!! use 'b0 or 32'b0
reg temp = 1'b0;
always@(posedge clk)
begin
count <= count + 1'b1;
if(count[7] == 1'b1)
begin
nextstate <= 1'b1;
end
if(count[7] == 1'b0)
begin
nextstate <= 1'b0;
end
end
// !!!! This is BAD! you should stay in the one clock domain
always@(posedge nextstate)
begin
state <= state + 1'b1;
if(state == 8'b00001010)
begin
state <= 8'h00;
end
if(state == 10)
begin
//increment channel count
channelstate <= channelstate + 1'b1;
end
end
always@(posedge clk)
begin
case(state)
0 : begin
data <= {8'h00,24'h 000000};
ReadWriteNot <= 0;
end
1 :data <= {8'h01,24'h 000000};
2 :data <= {8'h53,24'h 000000};
3 :data <= {8'h02,24'h 000000};
4 : begin
case(channelstate)
0 :data <= {8'h86,24'h 000000};
1 :data <= {8'h96,24'h 000000};
2 :data <= {8'hA6,24'h 000000};
3 :data <= {8'hB6,24'h 000000};
4 :data <= {8'hC6,24'h 000000};
default :data <= {8'h86,24'h 000000};
endcase
end
5 :data <= {8'h44,24'h 000000};
6 :begin//read 24 bits of data
ReadWriteNot <= 1;
ReceivingData <= 1; // !!!! who sets this back to 0????
ReadStart <= 1;
end
7: begin
data <= 32'h00000000; //nop
ReadStart <= 0;
end
8: begin
if(channelstate == 4)
begin
ADCresetn <= 1'b0;//reset
end
end
9: begin
if(channelstate == 4)
begin
ADCresetn <= 1'b1;
end
end
10: begin
data <= 32'h00000000; //nop
if(channelstate >= 4)
begin
channelstate <= 8'hFF;
end
end
default : data <= 32'h00000000;
endcase
end
always@(posedge clk)
begin
if(ReceivingData == 1)
begin
if(ReadDone == 1)
begin
if(state == 6)
begin
case(channelstate)
8'h00 :AnalogIData0[23:0] <= DataRead[23:0];
8'h01 :AnalogIData1[23:0] <= DataRead[23:0];
8'h02 :AnalogIData2[23:0] <= DataRead[23:0];
8'h03 :AnalogIData3[23:0] <= DataRead[23:0];
8'h04 :AnalogIData4[23:0] <= DataRead[23:0];
default :temp <= 1'b1;
endcase
end
end
end
end
always@(clk)
begin
ADCsclk <= clk; // !!!! should be =
end
SPI SPI_0(ReadWriteNot,clk, ADCdin, ADCdout, data, nextstate, ReadStart, DataRead, WriteDone, ReadDone,8, 24, CS, Ready, Reset,ADCcsn);
endmodule
Hope this helps!
John Providenza
/6 
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