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我正在研究PSoC SESESEI博客上的数据路径,我想知道: 在Verilog中,有移位、加法等功能,这些函数是相同的函数。 数据路径提供的。那么使用数据路径的优点是什么呢?是不是那个 Verilog合成器不使用数据路径吗?即一个纯粹的Verilog实现 使用UDB的效率较低,因为它不使用数据路径吗? 雨果 以上来自于百度翻译 以下为原文 Hi, I am studying the datapath on the PSoC Sensei blog at the moment, and I was wondering: In Verilog, there are functions such as shifting, adding, etc. These are the same functions that the datapath provides. What then is the advantage of using the datapath? Is it that the datapath is not used by the Verilog synthesizer? I.E. A pure Verilog implementation makes less efficient use of the UDB, because it does not use the datapath? Hugo |
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嗨,雨果,
编写Verilog代码将使用UDB中可用的PLD实现组合或时序逻辑。 但是,可以通过使用数据路径工具来利用UDB中可用的数据路径。这是使用UDBS的更强大的方法,因为数据路径具有它自己的ALU,它可以进行8次算术和逻辑运算。数据通路具有FIFO、累加器和数据寄存器。除此之外,还有硬件比较器,它将比较累加器的值与数据寄存器。这主要与核心并行工程(8051/ARM的PSoC 3/5 m3),从而改善现有的数字资源的利用。 以上来自于百度翻译 以下为原文 Hi Hugo, Writing just Verilog code will implement the combination or sequential logic using the PLDs available in UDB. However, the Datapath available in UDB can be utilized by using the Datapath Tool. This is much more powerful way of using the UDBs as Datapath has an ALU of it's own which can do 8 arithmetic and logical operations. A datapath has FIFO, Accumulator and Data Register. Apart from this, there are also hardware comparators which will compare the value of the Accumulator with Data Regsiters. This works in parallel with the main core (8051 / ARM Cortex M3 of PSoC 3/5), thereby improving the utilization of the available digital resources. |
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我可以使用DATAPATH使用ALU来添加两个字节。
但是我也可以使用Verilog添加两个字节,不是吗? 在Verilog中有缺点吗? 在数据路径中做这件事有什么好处吗? 雨果 以上来自于百度翻译 以下为原文 I can use the datapath to add two bytes together using the ALU. But I can also add two bytes using Verilog, can't I ? Is there a disadvantage to doing it in Verilog? Is there an advantage to doing it in the datapath? Hugo |
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差别在于大小。在Verilog中实现PMW将占用大部分可用的逻辑。使用DATAPATIT仅是单个块。
ALU与状态机结合构成一个小的处理器。 在PSoC1中,决定除了模拟列和数字输出行上的LUT之外,没有可编程逻辑。这是因为我们负担不起空间可编程逻辑的需要。记住,FPGA的成本psoc1卖10倍。我们认为我们有大多数单片机peripherials覆盖直到第二周PSoC进入从四轴decodered生产有人问。(该死!) 在PSoC3 / 5就决定我们不可能覆盖所有的perepherial你们想和thatprogrammable logicwas要求。设计师也不想thatfpgaswould需要开销。数据路径是一个很好的折衷方案。 你要记住,微处理器最初设计使逻辑设计易于。早在70年代初,数字化设计是SSI chipsor定制芯片。数字设计的表现,就不会有enoughdigital工程师工作的迅速增加。该解决方案是一个可编程时序逻辑器件或微处理机。如果我没记错的话,英特尔会给他们免费如果你从他们那里买了你的ROM和RAM。 我承认,线路路径PSoC3 / 5我最喜欢的部分,我认为一个模拟的家伙。 戴夫范斯 以上来自于百度翻译 以下为原文 The difference is size. An implementation of a PMW in verilog would take up most of the available logic. With a datapath it is only a single block. The ALU conbined with a state machine makes a small little processor. In PSoC1, it was decided to not have programmable logic other than the LUTs on the analog columns and digtal output rows. That was because we could not afford the space programmable logic would require. Remeber FPGAs sell for as much as 10 times the cost of a PSoC1. We thought we had most microcontroller peripherials covered until about the second week PSoC went into production someone asked from a quad shaft decodered. (damn!) On PSoC3/5 it was decided that we could never cover all the perepherial that you guys wanted and that programmable logic was required. The designers didn;t want the overhead that FPGAs would require. The data path is a good compromise. You have to remember that the microprocessor was originally desgned to make logic design easiler. Back in the early 70s, digital design was either SSI chips or a custom chip. With the rapid increase of digital designs it became apparrent that there would not be enough digital engineer to to the work. The solution was a programable sequencal logic device or a micro-processor. If I remember correctly, Intel would give them away for free if yyou bought your ROM and RAm from them. I will admit that the dath paths are my favorite part of PSoC3/5 and I am consider an analog guy. Dave Van Ess |
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此外,数据路径配置被保存在SRAM THA在CPU存储器空间中。随着CPU、DMA和内存空间的宽频带的力量,你现在有了一个动态配置的系统。这一结果将至少在5年内没有得到充分的探索。伙计们!你被赋予了做其他人以前没有做过的事情的机会。时间可分配的硬件。200%~300%的硬件利用率。神经类型设计。这些想法是无精打采的。当人们问他们为什么要使用PARS的时候,7HC芯片花费了9美分。
你被提供给定义未来逻辑设计的机会。该死,做这件事的工具还没有写完呢! 戴夫范斯 以上来自于百度翻译 以下为原文 Also the datapath configurations are held in SRAM tha is in the CPU memory space. With the power of the CPU, DMA , and the wide bandwith of the memory space you now have a dynamicly configured system. The results of this will not be fully explored for at least 5 more years. Guys! you are being given an oppertunity to do things no one else has done before. Time allocatable hardware. 200%- 300% utilization of hardware. Neuro type designs. The ideas are linitless. Remainds me when people asked why they should use PALs went 74HC chips cost 9 cents. You are being offered to the chance to define how logic is designed in the future. Hell, the tools to do this haven't even been written yet! Dave Van Ess |
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谢谢戴夫,
这是一个很好的答案!因此,您可以在verilog中完成所有这些ALUTHORKS,但是如果您只使用一个数据路径,它将使用更多的硬件。 我猜想这是双真(或OcTrue true),因为数据路径可以覆盖单个块中的8个函数。 雨果 以上来自于百度翻译 以下为原文 Thanks Dave, That was a great answer! So you could do all of those ALU functions in Verilog, but it would use much more hardware that if you just used a datapath. I guess that's doubly true (or octally true) because the datapath can cover 8 functions in a single block. Hugo |
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我刚才写了一篇文章,也许这会有帮助?
HTTP://www. EETim.COM/Debug /嵌入式/421555/WHYYU嵌入式控制器MY-NOT-NET-A CPU 以上来自于百度翻译 以下为原文 I wrote an article on this a while ago, maybe this will help? http://www.eetimes.com/design/embedded/4215555/Why-your-embedded-controller-may-not-need-a-CPU |
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谢谢。伟大的文章。
事实上,如果你想要的话,你可以把它们变成特殊用途的CPU。 雨果 以上来自于百度翻译 以下为原文 Thanks. Great article. So, in fact, you could probably turn them into special purpose CPUs if you wanted? Hugo |
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对。ILIKE的观点是计算PSoC的“处理器”数量:
CPU,DMAC,DFB,+ 24数据通路=27。但我们还没有完成: 在PLDs的状态机中,只有可用的UDBREST限制。但我们还没有完成: 也可以在模拟域中进行处理,例如使用混频器模式中的SC/CTBULD进行模拟乘法。 所以我通常说我们在PSoC3/ 5中有27个“处理器”,所以不要像传统MCU那样使用CPU。 以上来自于百度翻译 以下为原文 Yes. The way I like to view it is to count the number of "processors" in PSoC: CPU, DMAC, DFB, + 24 datapaths = 27. But we're not done yet: State machines in PLDs, number is limited only by available UDB resources. But we're still not done: Processing can also be done in the analog domain, e.g. using a SC/CT block in mixer mode to do analog multiplication. So I usually state that we have 27+ "processors" in PSoC 3/5, and so don't just use the CPU like one would in traditional MCUs. |
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回到过去,我们用OP AMP制造模拟计算机。有四个独立和四个CT-SC块opAMPS,这使得八以上。
PSoC Rocks,我的朋友们! 戴夫 以上来自于百度翻译 以下为原文 Back in the day we used to make analog computers with op amps. With four stand alone and four CT-SC block opamps, that makes eight more. PSoC Rocks my friends! Dave |
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