寄存器中的RAM合成而不是LUT

trounds写道：
感谢您及时的回复。
我只指定了一个初始条件，它是作为模拟的一部分生成的。
代码特定的合成没有初始条件。
为什么软件不知道这个？
您在此主题的第一篇文章中的代码看起来是正确的。
您确定在合成选项中正确设置了通用吗？
我假设SIM_ENB常量由实体的端口列表中的泛型设置，我进一步假设所讨论的实体不是FPGA设计的顶级。
您必须确保通用过滤器一直到层次结构的顶部，因此可以在综合和模拟选项中进行设置。
否则，工具将采用默认值（从您发布的代码中不清楚），老实说，我不知道在没有默认情况下会发生什么。
我的猜测是综合工具实际上使用的是SIM_RESULT_RAM。
值得一提的是：当你推断出一个内存时，模拟工具并不神奇地知道你的代码引用了一个特定的库元素。
它只是模拟您编码的内容。
最后，鲍勃对初始化器的建议应该是正确的。
所以类似于： 
type lutram_t是std_logic_vector的数组（0到15）（47 downto 0）; 
signal lutram：lutram_t：=（others =>（others =>'0'））;
-  
signal addr：自然范围0到15; 
signal foo：std_logic_vector（47 downto 0）; 
u_lutram：process（clk）是 
开始 
如果rising_edge（clk）那么 
如果我们='1'那么 
LUTRAM（地址） 
万一; 
万一; 
结束过程u_lutram;
那个做得好。
----------------------------是的，我这样做是为了谋生。
在原帖中查看解决方案



以下为原文

trounds wrote:
Thanks for the quick response.  I only specify an initial condition with this is generated as part of simulation.  There is no initial condition for the code specific to synthesis.  Why doesn't the software know this?

Your code in the first post in this thread looks correct.
 
Are you sure you set the generic properly in the synthesis options? I assume that the SIM_ENB constant is set by a generic in the entity's port list, and I futher assume that the entity in question isn't the top level of the FPGA design.
 
You have to make sure that the generic filters all the way up to the top of the hierarchy, so it can be set in the synthesis and simulation options. Otherwise, the tools will assume the default (which isn't clear from the code you posted) and honestly, I don't know what happens in absence of a default. 
 
My guess is that the synthesis tool is actually using the SIM_RESULT_RAM.
 
And for what it's worth: when you infer a memory, the simulation tool doesn't magically know that your code refers to a specific library element. It just simulates exactly what you code. 
 
Finally, what Bob suggests about an initializer should be correct. So something like: 
 
    type lutram_t is array (0 to 15) of std_logic_vector(47 downto 0);
    signal lutram : lutram_t := (others => (others => '0')); -- <<== this is the initializer
    signal addr   : natural range 0 to 15;
    signal foo    : std_logic_vector(47 downto 0);
 
    u_lutram : process (clk) is
    begin
        if rising_edge(clk) then 
            if we = '1' then
                lutram(addr) <= foo;
            end if;
        end if;
    end process u_lutram;
 
that oughta do it. 
----------------------------Yes, I do this for a living.View solution in original post

汤姆，
如果指定初始条件或需要复位，则不能使用LUTRAM（因为它没有复位/设置，并且在配置时始终从0开始）。
Austin Lesea主要工程师Xilinx San Jose



以下为原文

Tom,

If you specify an initial condition, or require a reset, LUTRAM can not be used (as it has no reset/set, and always starts out at 0's when configured).
 
 
Austin Lesea
Principal Engineer
Xilinx San Jose

感谢您及时的回复。
我只指定了一个初始条件，它是作为模拟的一部分生成的。
代码特定的合成没有初始条件。
为什么软件不知道这个？



以下为原文

Thanks for the quick response.  I only specify an initial condition with this is generated as part of simulation.  There is no initial condition for the code specific to synthesis.  Why doesn't the software know this?

这并没有解决trounds的主要问题，但它确实清除了似乎是错误的表示，不应该让它站起来。
奥斯汀写道：
如果指定初始条件或需要复位，则不能使用LUTRAM（因为它没有复位/设置，并且在配置时始终从0开始）。
复位引脚确实会排除LUT-RAM，但指定初始条件应该不是障碍。
如果不是具有指定初始条件的LUT-RAM，那么FPGA设计中的所有逻辑LUT是什么？
@trounds：
为了消除路径中的障碍，具有初始化状态（但没有归零功能）的16x48位分布式RAM是否满足综合和仿真要求，并可能帮助您继续设计？
- 鲍勃埃尔金德
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以下为原文

This doesn't address the primary problem for trounds, but it does clear up what appears to be a mistaken representation which should not be left to stand.
 
Austin wrote:
 
If you specify an initial condition, or require a reset, LUTRAM can not be used (as it has no reset/set, and always starts out at 0's when configured).
 
A reset pin will indeed preclude LUT-RAM, but specifiying an initial condition should be no obstacle.  What are all the logic LUTs in an FPGA design, if not LUT-RAM with a specified initial condition?
 
@trounds:
 
In the interest of removing a roadblock in your path, would a 16x48-bit distributed RAM with initialised state (but no reset-to-zero capability) satisfy both synthesis and simulation requirements, and possibly help you move forward with your design?
 
-- Bob Elkind
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是的，这将满足两个条件。
我只需要某种初始状态进行模拟。
我不关心状态在合成中是什么，因为我使用它进行低通滤波，它最终将在现实世界的应用程序中清空。
当我设置SIM_ENB = FALSE时，我很惊讶工具正在查看与模拟相关的代码。
我本以为会忽视它。
我在这个FPGA中有相当多的滤波器，纠正这个问题使我对XC6SLX45的利用率从73％降低到31％。
我使用的是Webpack工具的13.3版。
我以前忽略了这一点。
我知道13.4已经出局但我尚未升级。



以下为原文

Yes that would satisfy both conditions.  I only need some sort of initial state for simulation.  I don't care what the states are in synthesis since I'm using this for low pass filtering and it will eventually flush out in the real world application.
 
I'm just surprised that the tools are looking at the code related to simulation when I set SIM_ENB = FALSE.  I would have thought it would disregard it.  I have quite a few filters in this FPGA and correcting this problem reduced my utilization of an XC6SLX45 from 73% down to 31%.
 
I am using version 13.3 of the Webpack tools.  I had neglected to mention that before.  I know 13.4 is out but I haven't upgraded yet.
 

我刚刚尝试去除模拟的RESET ='1'测试，并将变量留在STARTUP中。
它没有帮助。
可以肯定的是，我没有陷入困境。
我只是在报告它表现得不像我认为的那样。
我知道如何解决这个问题;
我已选择注释掉代码的模拟部分并添加一个断言语句，如果SIM_ENB = TRUE则会发出警告，所以我记得取消注释模拟代码。
我还可以从Coregen工具中专门实例化一个简单的RAM。
我更倾向于推断这种逻辑对于未来的变化尽可能灵活。



以下为原文

I have just tried getting rid of the RESET = '1' test for simulation and left in the variable for STARTUP.  It didn't help.
 
To be sure, I'm not stuck. I'm just reporting that it isn't behaving like I think it should.
 
I know how to get around this problem; I have chosen to comment out the simulation section of code and add in an assert statement that warns me if SIM_ENB = TRUE so I remember to uncomment the code for simulation.  I could also specifically instantiate a simple RAM from the Coregen tool.    I prefer to infer this logic to be as flexible as possible for future changes.
 
 

我只需要某种初始状态进行模拟。
初始状态要求已经满足，无需额外努力。
配置完成后，分布式RAM默认为包含零的所有位置。
对于分布式RAM的非零初始状态，您有（至少）三种选择：
Distributed Memory Generator coregen向导会提示您输入.COE（系数）文件来定义初始内容。
使用稍微通用的HDL构造来推断RAM，结合用于指定RAM的初始内容和合成样式（例如分布式）的合成指令。
如果使用设备原语（例如Spartan-3E RAM16x2S原语），则可以使用.INIT属性在实例化原语的代码中在线指定初始内容。
ISE语言模板中的示例（单击ISE Navigator中的灯泡图标）：
RAM16X2S＃（。INIT_00（16'h0000），// RAM的位0的初始内容.INIT_01（16'h0000）// RAM的第1位的初始内容）RAM16X2S_inst（.O0（O0），// RAM数据[
0]输出.O1（O1），// RAM数据[1]输出.A0（A0），// RAM地址[0]输入.A1（A1），// RAM地址[1]输入.A2（A2）
，// RAM地址[2]输入.A3（A3），// RAM地址[3]输入.D0（D0），// RAM数据[0]输入.D1（D1），// RAM数据[1]
输入.WCLK（WCLK），//写时钟输入.WE（WE）//写使能输入）; 
参数RAM_WIDTH =;
参数RAM_ADDR_BITS =;
（* RAM_STYLE =“{AUTO | DISTRIBUTED | PIPE_DISTRIBUTED}”*）reg [RAM_WIDTH-1：0] [（2 ** RAM_ADDR_BITS）-1：0];
电线[RAM_WIDTH-1：0];
[RAM_ADDR_BITS-1：0];
[RAM_WIDTH-1：0];
总是@（posedge）if（）[];
assign = [];
进一步阅读：XST用户指南（UG627）的整个部分标题为初始化RAM编码示例。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
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以下为原文

I only need some sort of initial state for simulation.
 
The initial state requirement is already met with no additional effort.  A distributed RAM defaults to all locations containing zero after configuration is completed.  For non-zero initial state of distributed RAM, you have (at least) three choices:
 

• The Distributed Memory Generator coregen wizard prompts you for a .COE (coefficients) file to define initial contents.
  

• Use somewhat generic HDL constructs for inferring RAM, combined with synthesis directives for specifying initial contents and synthesised style (e.g.  distributed) of RAM.
  

• If you use a device primitive (for example the Spartan-3E RAM16x2S primitive), the initial contents may be specified in-line in your code where the primitive is instantiated, using .INIT attributes.
  

 
Examples from the ISE  Language Templates (click on the light-bulb icon within ISE Navigator):
 
RAM16X2S #(
      .INIT_00(16'h0000), // Initial contents of bit 0 of RAM
      .INIT_01(16'h0000)  // Initial contents of bit 1 of RAM
   ) RAM16X2S_inst (
      .O0(O0),     // RAM data[0] output
      .O1(O1),     // RAM data[1] output
      .A0(A0),     // RAM address[0] input
      .A1(A1),     // RAM address[1] input
      .A2(A2),     // RAM address[2] input
      .A3(A3),     // RAM address[3] input
      .D0(D0),     // RAM data[0] input
      .D1(D1),     // RAM data[1] input
      .WCLK(WCLK), // Write clock input
      .WE(WE)      // Write enable input
   );
 
 
 
   parameter RAM_WIDTH = ;
   parameter RAM_ADDR_BITS = ;

   (* RAM_STYLE="{AUTO | DISTRIBUTED | PIPE_DISTRIBUTED}" *)
   reg [RAM_WIDTH-1:0] [(2**RAM_ADDR_BITS)-1:0];

   wire [RAM_WIDTH-1:0] ;

   [RAM_ADDR_BITS-1:0]

;
   [RAM_WIDTH-1:0] ;

   always @(posedge )
      if ()
         [

] <= ;

   assign = [

];


 
Further reading:  XST User Guide (UG627) has an entire section titled Initializing RAM Coding Examples.
 
-- Bob Elkind
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是的，我同意，但模拟器似乎不知道零驱动器的初始/上电配置，因此它在RAM中给出了未定义的值，因此我无法模拟滤波器操作。
滤波器的新值基于先前的值（它是IIR滤波器），因此除非我强制模拟某个值，否则它永远不会消失。



以下为原文

Yes, I agree, but the simulator doesn't seem to know about the initial/powerup configuration of zero states so it gives me undefined values in the RAM and so I cannot simulate the filter operation.  The new values of the filter are based on previous values (it is an IIR filter) so it never settles out unless I force the simulation to some value.
 

值得一提的是，以下快速实验成功合成了（ISE 13.4）带有24个Spartan-6 LUT的16x48单端口SRAM（每个LUT 2位，因为Spartan-6 LUT为64x1或32x2）。
模块s6_forum_top（输入inclk100m，输入[3：0] lut_addr，输入[47：0] lut_din，输入lut_we，输出[47：0] lut_dout）;（* RAM_STYLE =“DISTRIBUTED”*）reg [47：0] forum_lutram
[15：0];
//深16个字，48个数据位宽
initial begin forum_lutram [0] = 48'h0000_0000_0000;
forum_lutram [1] = 48'h0001_0000_0001;
forum_lutram [2] = 48'h0002_0000_0002;
forum_lutram [3] = 48'h0003_0000_0003;
forum_lutram [4] = 48'h0004_0000_0004;
forum_lutram [5] = 48'h0005_0000_0005;
forum_lutram [6] = 48'h0006_0000_0006;
forum_lutram [7] = 48'h0007_0000_0007;
forum_lutram [8] = 48'h0000_0008_0008;
forum_lutram [9] = 48'h0000_0009_0009;
forum_lutram [10] = 48'h0000_000A_000A;
forum_lutram [11] = 48'h0000_000B_000B;
forum_lutram [12] = 48'h0000_000C_000C;
forum_lutram [13] = 48'h0000_000D_000D;
forum_lutram [14] = 48'h0000_000E_000E;
forum_lutram [15] = 48'h0000_000F_000F;结束
总是@（posedge inclk100m）如果（lut_we）forum_lutram [lut_addr]指定lut_dout = forum_lutram [lut_addr];
endmodule
我没有打扰内存字深度和数据宽度的参数，但这应该没问题。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
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以下为原文

For what it's worth, the following quick experiment successfully synthesised (ISE 13.4) a 16x48 single port SRAM with 24 Spartan-6 LUTs (2 bits per LUT, as Spartan-6 LUTs are either 64x1 or 32x2).
 
module s6_forum_top (
    input              inclk100m,
    input    [3:0]     lut_addr,
    input    [47:0]    lut_din,
    input              lut_we,
    output   [47:0]    lut_dout
);

(* RAM_STYLE="DISTRIBUTED" *)
reg [47:0] forum_lutram [15:0]; // 16 words deep, 48 data bits wide
 
initial begin
  forum_lutram[0] = 48’h0000_0000_0000;
  forum_lutram[1] = 48’h0001_0000_0001;
  forum_lutram[2] = 48’h0002_0000_0002;
  forum_lutram[3] = 48’h0003_0000_0003;
  forum_lutram[4] = 48’h0004_0000_0004;
  forum_lutram[5] = 48’h0005_0000_0005;
  forum_lutram[6] = 48’h0006_0000_0006;
  forum_lutram[7] = 48’h0007_0000_0007;
  forum_lutram[8] = 48’h0000_0008_0008;
  forum_lutram[9] = 48’h0000_0009_0009;
  forum_lutram[10] = 48’h0000_000A_000A;
  forum_lutram[11] = 48’h0000_000B_000B;
  forum_lutram[12] = 48’h0000_000C_000C;
  forum_lutram[13] = 48’h0000_000D_000D;
  forum_lutram[14] = 48’h0000_000E_000E;
  forum_lutram[15] = 48’h0000_000F_000F;
end
 
always @(posedge inclk100m)
    if (lut_we) forum_lutram[lut_addr] <= lut_din;

assign lut_dout = forum_lutram[lut_addr];
 
endmodule
 
I didn't bother with parameters for memory word depth and data width, but this should be no problem.
 
-- Bob Elkind
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是的，我同意，但模拟器似乎不知道零驱动器的初始/上电配置，因此它在RAM中给出了未定义的值，因此我无法模拟滤波器操作。
这似乎很奇怪。
您是否尝试过具有相同结果的行为和结构模拟模型？
只是猜测......
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
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以下为原文

Yes, I agree, but the simulator doesn't seem to know about the initial/powerup configuration of zero states so it gives me undefined values in the RAM and so I cannot simulate the filter operation.
 
This seems like odd behaviour.  Have you tried both behavioural and structural simulation models with identical results?  Just a wild guess....
 
-- Bob Elkind
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1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
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5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
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8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

trounds写道：
感谢您及时的回复。
我只指定了一个初始条件，它是作为模拟的一部分生成的。
代码特定的合成没有初始条件。
为什么软件不知道这个？
您在此主题的第一篇文章中的代码看起来是正确的。
您确定在合成选项中正确设置了通用吗？
我假设SIM_ENB常量由实体的端口列表中的泛型设置，我进一步假设所讨论的实体不是FPGA设计的顶级。
您必须确保通用过滤器一直到层次结构的顶部，因此可以在综合和模拟选项中进行设置。
否则，工具将采用默认值（从您发布的代码中不清楚），老实说，我不知道在没有默认情况下会发生什么。
我的猜测是综合工具实际上使用的是SIM_RESULT_RAM。
值得一提的是：当你推断出一个内存时，模拟工具并不神奇地知道你的代码引用了一个特定的库元素。
它只是模拟您编码的内容。
最后，鲍勃对初始化器的建议应该是正确的。
所以类似于： 
type lutram_t是std_logic_vector的数组（0到15）（47 downto 0）; 
signal lutram：lutram_t：=（others =>（others =>'0'））;
-  
signal addr：自然范围0到15; 
signal foo：std_logic_vector（47 downto 0）; 
u_lutram：process（clk）是 
开始 
如果rising_edge（clk）那么 
如果我们='1'那么 
LUTRAM（地址） 
万一; 
万一; 
结束过程u_lutram;
那个做得好。
----------------------------是的，我这样做是为了谋生。



以下为原文

trounds wrote:
Thanks for the quick response.  I only specify an initial condition with this is generated as part of simulation.  There is no initial condition for the code specific to synthesis.  Why doesn't the software know this?

Your code in the first post in this thread looks correct.
 
Are you sure you set the generic properly in the synthesis options? I assume that the SIM_ENB constant is set by a generic in the entity's port list, and I futher assume that the entity in question isn't the top level of the FPGA design.
 
You have to make sure that the generic filters all the way up to the top of the hierarchy, so it can be set in the synthesis and simulation options. Otherwise, the tools will assume the default (which isn't clear from the code you posted) and honestly, I don't know what happens in absence of a default. 
 
My guess is that the synthesis tool is actually using the SIM_RESULT_RAM.
 
And for what it's worth: when you infer a memory, the simulation tool doesn't magically know that your code refers to a specific library element. It just simulates exactly what you code. 
 
Finally, what Bob suggests about an initializer should be correct. So something like: 
 
    type lutram_t is array (0 to 15) of std_logic_vector(47 downto 0);
    signal lutram : lutram_t := (others => (others => '0')); -- <<== this is the initializer
    signal addr   : natural range 0 to 15;
    signal foo    : std_logic_vector(47 downto 0);
 
    u_lutram : process (clk) is
    begin
        if rising_edge(clk) then 
            if we = '1' then
                lutram(addr) <= foo;
            end if;
        end if;
    end process u_lutram;
 
that oughta do it. 
----------------------------Yes, I do this for a living.

谢谢你们两个！我应该考虑正确设置初始化程序，而不是在我想模拟时编写specialVHDL代码。
这就像模拟和合成的魅力，我可以摆脱SIM_ENB泛型。
虽然我很惊讶，当SIM_ENB = FUE时，当SIM_ENB = TRUE时，包含少量将RAM初始化为0的行会影响合成代码。
我原以为它会完全被忽略。
这不是条件代码生成的全部意义吗？
顺便说一句，这是一个修辞问题，而索诺的回答是需要的。
干杯全都。



以下为原文

Thank you both!  I should have thought of setting the initializer properly instead of writing special VHDL code to do it when I wanted to simulate.  That works like a charm for simulation and synthesis and I can get rid of the SIM_ENB generic.
 
Though I am still surprised that the inclusion of the few lines that initialize the RAM to 0's when SIM_ENB=TRUE affects the synthesized code when SIM_ENB=FALSE.  I would have thought it would be ignored entirely.  Isn't that what conditional code generation is all about?  BTW that's a rhetorical question so no answer is needed.
 
Cheers all.
 
 

trounds写道：
虽然我很惊讶，当SIM_ENB = FUE时，当SIM_ENB = TRUE时，包含少量将RAM初始化为0的行会影响合成代码。
我原以为它会完全被忽略。
这不是条件代码生成的全部意义吗？
顺便说一句，这是一个修辞问题，而索诺的回答是需要的。
我仍然认为SIM_ENB的设置方式不是你认为它应该是FALSE的情况。
检查综合报告。
----------------------------是的，我这样做是为了谋生。



以下为原文

trounds wrote:
 
Though I am still surprised that the inclusion of the few lines that initialize the RAM to 0's when SIM_ENB=TRUE affects the synthesized code when SIM_ENB=FALSE.  I would have thought it would be ignored entirely.  Isn't that what conditional code generation is all about?  BTW that's a rhetorical question so no answer is needed.
 

I still think the SIM_ENB isn't being set the way you think it is for the case where it's supposed to be FALSE. Check your synthesis reports.
----------------------------Yes, I do this for a living.