Virtex5 dcm使用情况

S，
根本不要使用DCM！
只需使用计数器将50 MHz的频率除以40至1.25 MHz。
在如此低的频率下，您没有时间问题应该是一个问题（根本不需要DCM）。
只需确保使用40计数器的同步除法，占空比约为50-50（您可能希望使用除以20的计数器，然后除以2）。
Austin Lesea主要工程师Xilinx San Jose



以下为原文

s,
 
Do not use a DCM at all!  Just use a counter to divide by 40 the 50 MHz down to 1.25 MHz.  At such a low frequency, you have no timing concerns that should be an issue (do not need a DCM at all).  Just be sure to use a synchronous divide by 40 counter, with a roughly 50-50 duty cycle (you may wish to use a divide by twenty counter, and then divide by 2).
 
 
Austin Lesea
Principal Engineer
Xilinx San Jose

我试图从50Mhz外部时钟信号到FPGA获得1.25Mhz时钟信号，以运行一个自由运行的二进制计数器。
例：
模块suni（ 
输入clock50，// 50MHz输入时钟 
输出reg [9：0]计数器= 0 //自由运行计数器，计数率为1.25MHz
）
reg [5：0] scaler = 0;
//将50MHz除以40
总是@（posedge clock50） 
if（scaler> = 6'd39）scaler // count到39，然后换行为0 
否则缩放器
总是@（posedge clock50） 
if（scaler == 0）计数器//每40个时钟周期计数一次（1.25MHz）
endmodule
这有意义吗？
这不会给你一个1.25MHz的时钟信号，但它确实给你一个自由运行的二进制计数器，其计数为1.25MHz。
在之前的帖子中，您使用的是Spartan 2（使用ISE 10）或Spartan 3E。
您现在使用的是Virtex-5设备吗？
学习使用Verilog或VHDL（非原理图捕获）以及ISE 13或ISE 14支持的目标设备对您有好处。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

I am trying to get a 1.25Mhz clock signal from 50Mhz external clock signal to FPGA to run a free running binary counter.
 
Example:
 
module suni (
  input clock50,  // 50MHz input clock
  output reg [9:0] counter = 0  // free-running counter, count rate is 1.25MHz
)
 
reg [5:0] scaler=0;  // divide 50MHz by 40
 
always @(posedge clock50)
  if (scaler >= 6'd39) scaler <= 0;  // count to 39, then wrap to 0
  else                 scaler <= scaler + 1;
 
always @(posedge clock50)
  if (scaler == 0) counter <= counter + 1;  // count once every 40 clock cycles (1.25MHz)
 
endmodule
 
Does this make sense?  This doesn't give you a 1.25MHz clock signal, but it does give you a free-running binary counter which counts at 1.25MHz rate.
 
In previous posts, you were using either Spartan 2 (with ISE 10) or Spartan 3E.  Are you now using a Virtex-5 device?
It would be good for you to be learning to use either Verilog or VHDL (not schematic capture), and a target device which is supported by ISE 13 or ISE 14.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

模拟它，看看它做了什么....
我认为它没有你想要的，你没有1.5 MHz时钟的输出....
Austin Lesea主要工程师Xilinx San Jose



以下为原文

Simulate it, and look at what it does....

I don't think it does what you want, and you do not have an output for your 1.5 MHz clock....
Austin Lesea
Principal Engineer
Xilinx San Jose

>任何人都可以帮助我吗？不是来自那个小的（伪）代码片段......
------------------------------------------“如果它不起作用
模拟，它不会在板上工作。“



以下为原文

> Can anybody help me on this?

Not from that small a (pseudo-)code snippet...

------------------------------------------
"If it don't work in simulation, it won't work on the board."

我使用以下代码生成1250Mhz时钟，然后将其用作另一个计数器的时钟信号。
过程（CLK，RST）
开始
@rising边缘
如果步骤= 40那么
步骤）帮助你更好。



以下为原文

I generated the 1250Mhz clock using a following code and then used that as a clock signal to another counter.
 
process(clk,rst)
begin
@rising edge
if step=40 then
step<=0;
clk1250<=1;
else
step<=step+1;
clk1250<=0;
end if;
when i simulated this code it worked ok.
but when i try to synthezise this i get following error;
 
"formal clk1250 with no default value must be associated with actual value"
Can anybody help me on this?
 
 
 
Please post enough code(top-level wrapper in which you are instantiating this module and port clk1250 ) to help you better.
 
 

我附上了模块的完整代码。
谢谢Binary Time.text 3 KB



以下为原文

I've attatched the complete code of the module. Thanks
            BinaryTime.txt ‏3 KB

我错过了什么吗？



以下为原文

am i missing anything on this?

我找到了这个问题。
我一直都是我的错。



以下为原文

I was able to find the issue. I was my mistake all along.