完善资料让更多小伙伴认识你,还能领取20积分哦, 立即完善>
你好,
我将使用Spartan 6,我将需要一个缓冲区(可能是几个缓冲区)来传入14位宽的字。 深度约为40000字,因此等于560 Kb。 设备XC6SLX45T具有2088 Kb max BRAM。 所以,我想知道我是否使用了大约70-90%的BRAM,整个过程不会减慢一点吗? Ignas 以上来自于谷歌翻译 以下为原文 Hello, I'm going to use Spartan 6 and I will need a buffer (likely few buffers) for incoming 14bit wide words. The depth will be about 40000 words so it equals to 560 Kb. Device XC6SLX45T has 2088 Kb max BRAM available. So, I'm wondering if I use about 70-90 % of BRAM, won't the entire process slow down a little bit?Ignas |
|
相关推荐
12个回答
|
|
你的问题是广泛而含糊的,这是适当的广泛和模糊的答案:
设计中的所有内容都可能影响设计的运行频率,包括BRAM。 您可以实现一种设计,该设计使用90%的器件可用Block RAM,同时保持Block RAM的全带宽(工作时钟频率)。 如果你相当小心,这应该不难实现。 这在很大程度上取决于您的其他设计。 使用90%的片上Block RAM和仅有20%的CLB资源的设计可能不是“拥挤”设计。 如果使用80%的CLB资源,则可能难以保持接近Block RAM的最大工作频率的工作时钟频率。 您设计的预期时钟频率是多少? 不要忽略CLB之间以及CLB和BRAM之间的互连延迟。 您在高带宽系统设计方面的经验如何,尤其是数据通路和流水线? 如果您有兴趣接近所选设备的工作频率限制,您的技能和才能将影响您的结果。 - 鲍勃埃尔金德 签名:新手的自述文件在这里:http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结:1。 阅读手册或用户指南。 你读过手册了吗? 你能找到手册吗?2。 搜索论坛(并搜索网页)以寻找类似的主题。 不要在多个论坛上发布相同的问题。 不要在别人的主题上发布新主题或问题,开始新的主题!5。 学生:复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。 提供有用的详细信息(请与网页,数据表链接).7。 您的代码中的评论不需要支付额外费用。 我没有支付论坛帖子的费用。 如果我写一篇好文章,那么我一无所获。 在原帖中查看解决方案 以上来自于谷歌翻译 以下为原文 Your question is broad and vague, and here is the appropriate broad and vague answer: Everything in your design may affect the operating frequency of your design, including the BRAMs. You can implement a design which uses 90% of the devices's available Block RAM while maintaining the full bandwidth (operating clock frequency) of the Block RAMs. If you are reasonably careful, this should not be difficult to achieve. This depends heavily on the rest of your design. A design which uses 90% of the on-chip Block RAM and only 20% of the CLB resources is probably NOT a 'congested' design. If 80% of the CLB resources are utilised, you might have considerable difficulty maintaining an operating clock frequency which approaches the max operating frequency of the Block RAM. What is the expected clock frequency for your design? Don't overlook the interconnect delays between CLBs, and between CLBs and BRAMs. How experienced are you in high-bandwidth system design, especially datapaths and pipelines? Your skills and talents will affect your outcome, if you are interested in approaching the operating frequency limits of your selected device. -- Bob Elkind SIGNATURE: README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369 Summary: 1. Read the manual or user guide. Have you read the manual? Can you find the manual? 2. Search the forums (and search the web) for similar topics. 3. Do not post the same question on multiple forums. 4. Do not post a new topic or question on someone else's thread, start a new thread! 5. Students: Copying code is not the same as learning to design. 6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please). 7. You are not charged extra fees for comments in your code. 8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.View solution in original post |
|
|
|
你指的是什么'过程'?
- 鲍勃埃尔金德 签名:新手的自述文件在这里:http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结:1。 阅读手册或用户指南。 你读过手册了吗? 你能找到手册吗?2。 搜索论坛(并搜索网页)以寻找类似的主题。 不要在多个论坛上发布相同的问题。 不要在别人的主题上发布新主题或问题,开始新的主题!5。 学生:复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。 提供有用的详细信息(请与网页,数据表链接).7。 您的代码中的评论不需要支付额外费用。 我没有支付论坛帖子的费用。 如果我写一篇好文章,那么我一无所获。 以上来自于谷歌翻译 以下为原文 To what 'process' are you referring? -- Bob Elkind SIGNATURE: README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369 Summary: 1. Read the manual or user guide. Have you read the manual? Can you find the manual? 2. Search the forums (and search the web) for similar topics. 3. Do not post the same question on multiple forums. 4. Do not post a new topic or question on someone else's thread, start a new thread! 5. Students: Copying code is not the same as learning to design. 6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please). 7. You are not charged extra fees for comments in your code. 8. I am not paid for forum posts. If I write a good post, then I have been good for nothing. |
|
|
|
例如,读取和写入BRAM?
实际上我对由于BRAM利用率高而出现的所有重大变化感兴趣。 也许有一些建议,例如没有达到90%的BRAM或类似的东西? 问候, Ignas 以上来自于谷歌翻译 以下为原文 For example reading from and writing to BRAM? Actually I'm interested in all significant changes, which appear because of high BRAM utilization. Maybe there are some kind of recommendations, for example not to reach 90% of BRAM or something like that? Regards, Ignas |
|
|
|
你的问题是广泛而含糊的,这是适当的广泛和模糊的答案:
设计中的所有内容都可能影响设计的运行频率,包括BRAM。 您可以实现一种设计,该设计使用90%的器件可用Block RAM,同时保持Block RAM的全带宽(工作时钟频率)。 如果你相当小心,这应该不难实现。 这在很大程度上取决于您的其他设计。 使用90%的片上Block RAM和仅有20%的CLB资源的设计可能不是“拥挤”设计。 如果使用80%的CLB资源,则可能难以保持接近Block RAM的最大工作频率的工作时钟频率。 您设计的预期时钟频率是多少? 不要忽略CLB之间以及CLB和BRAM之间的互连延迟。 您在高带宽系统设计方面的经验如何,尤其是数据通路和流水线? 如果您有兴趣接近所选设备的工作频率限制,您的技能和才能将影响您的结果。 - 鲍勃埃尔金德 签名:新手的自述文件在这里:http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结:1。 阅读手册或用户指南。 你读过手册了吗? 你能找到手册吗?2。 搜索论坛(并搜索网页)以寻找类似的主题。 不要在多个论坛上发布相同的问题。 不要在别人的主题上发布新主题或问题,开始新的主题!5。 学生:复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。 提供有用的详细信息(请与网页,数据表链接).7。 您的代码中的评论不需要支付额外费用。 我没有支付论坛帖子的费用。 如果我写一篇好文章,那么我一无所获。 以上来自于谷歌翻译 以下为原文 Your question is broad and vague, and here is the appropriate broad and vague answer: Everything in your design may affect the operating frequency of your design, including the BRAMs. You can implement a design which uses 90% of the devices's available Block RAM while maintaining the full bandwidth (operating clock frequency) of the Block RAMs. If you are reasonably careful, this should not be difficult to achieve. This depends heavily on the rest of your design. A design which uses 90% of the on-chip Block RAM and only 20% of the CLB resources is probably NOT a 'congested' design. If 80% of the CLB resources are utilised, you might have considerable difficulty maintaining an operating clock frequency which approaches the max operating frequency of the Block RAM. What is the expected clock frequency for your design? Don't overlook the interconnect delays between CLBs, and between CLBs and BRAMs. How experienced are you in high-bandwidth system design, especially datapaths and pipelines? Your skills and talents will affect your outcome, if you are interested in approaching the operating frequency limits of your selected device. -- Bob Elkind SIGNATURE: README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369 Summary: 1. Read the manual or user guide. Have you read the manual? Can you find the manual? 2. Search the forums (and search the web) for similar topics. 3. Do not post the same question on multiple forums. 4. Do not post a new topic or question on someone else's thread, start a new thread! 5. Students: Copying code is not the same as learning to design. 6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please). 7. You are not charged extra fees for comments in your code. 8. I am not paid for forum posts. If I write a good post, then I have been good for nothing. |
|
|
|
brilas写道:
你好, 我将使用Spartan 6,我将需要一个缓冲区(可能是几个缓冲区)来传入14位宽的字。 深度约为40000字,因此等于560 Kb。 设备XC6SLX45T具有2088 Kb max BRAM。 所以,我想知道我是否使用了大约70-90%的BRAM,整个过程不会减慢一点吗? Ignas 你必须是数字电路设计的新手。 ----------------------------是的,我这样做是为了谋生。 以上来自于谷歌翻译 以下为原文 brilas wrote:You must be new to digital circuit design. ----------------------------Yes, I do this for a living. |
|
|
|
Ignas,
*你认为90%的BRAM利用率会影响性能? 你去年在这些论坛上发布了80多次。 您获得了哪些理解或洞察力,这表明您的表现可能会发生变化? 你必须是数字电路设计的新手。 我们每个人都曾经这样做过。 不知怎的,我们设法过度了解这种短暂的状态。 持久性有帮助吗? - 鲍勃埃尔金德 签名:新手的自述文件在这里:http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结:1。 阅读手册或用户指南。 你读过手册了吗? 你能找到手册吗?2。 搜索论坛(并搜索网页)以寻找类似的主题。 不要在多个论坛上发布相同的问题。 不要在别人的主题上发布新主题或问题,开始新的主题!5。 学生:复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。 提供有用的详细信息(请与网页,数据表链接).7。 您的代码中的评论不需要支付额外费用。 我没有支付论坛帖子的费用。 如果我写一篇好文章,那么我一无所获。 以上来自于谷歌翻译 以下为原文 Ignas, How do *you* think performance might be affected by 90% BRAM utilisation? You've posted to these forums 80+ times over the last year. What understanding or insight have you gained which suggests to you there might be a change in performance? You must be new to digital circuit design. This was true of each of us, at one time. Somehow we managed to ovecome this transient state. Persistence helps, perhaps? -- Bob Elkind SIGNATURE: README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369 Summary: 1. Read the manual or user guide. Have you read the manual? Can you find the manual? 2. Search the forums (and search the web) for similar topics. 3. Do not post the same question on multiple forums. 4. Do not post a new topic or question on someone else's thread, start a new thread! 5. Students: Copying code is not the same as learning to design. 6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please). 7. You are not charged extra fees for comments in your code. 8. I am not paid for forum posts. If I write a good post, then I have been good for nothing. |
|
|
|
eteam00写道:
您获得了哪些理解或洞察力,这表明您的表现可能会发生变化? 你必须是数字电路设计的新手。 我们每个人都曾经这样做过。 不知怎的,我们设法过度了解这种短暂的状态。 持久性有帮助吗? 我们没有开始使用巨型FPGA。 ----------------------------是的,我这样做是为了谋生。 以上来自于谷歌翻译 以下为原文 eteam00 wrote: We didn't start working with giant FPGAs. ----------------------------Yes, I do this for a living. |
|
|
|
我们没有开始使用巨型FPGA。
不能代表你说话,但Xilinx / ATT 3090a对我来说似乎相当巨大 - 特别是与3030a相比。 35页的OrCad(DOS)原理图。 我的前20个左右的FPGA设计基于3030a和3090a。 我使用了我可以拿到的最大包装:208针四角平板。 每当我为一些无法正常工作的事情而生气时,我就会召集一些名叫Peter Alfke的Xilinx技术支持人员,他会试着让我冷静下来。 在那些日子里,如果你没有学习FPGA编辑器(我忘记了当时所谓的那个),那你就是“死肉”(美国口语中的绝对术语)。 - 鲍勃'感谢回忆'Elkind 签名:新手的自述文件在这里:http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结:1。 阅读手册或用户指南。 你读过手册了吗? 你能找到手册吗?2。 搜索论坛(并搜索网页)以寻找类似的主题。 不要在多个论坛上发布相同的问题。 不要在别人的主题上发布新主题或问题,开始新的主题!5。 学生:复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。 提供有用的详细信息(请与网页,数据表链接).7。 您的代码中的评论不需要支付额外费用。 我没有支付论坛帖子的费用。 如果我写一篇好文章,那么我一无所获。 以上来自于谷歌翻译 以下为原文 We didn't start working with giant FPGAs. Can't speak for you, but the Xilinx/ATT 3090a seemed pretty huge to me at the time -- especially compared to the 3030a. 35 pages of OrCad (DOS) schematics. My first 20 or so FPGA designs were 3030a and 3090a based. I used the biggest package I could get my hands on: the 208-pin quad flatpak. Every time I got mad about something that wasn't working right, I called some tech support guy at Xilinx named Peter Alfke, and he would try to calm me down. In those days, if you didn't learn the FPGA editor (I forget what it was called back then), you were 'dead meat' (American colloquial term for being in hopeless circumstances). -- Bob 'thanks for the memories" Elkind SIGNATURE: README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369 Summary: 1. Read the manual or user guide. Have you read the manual? Can you find the manual? 2. Search the forums (and search the web) for similar topics. 3. Do not post the same question on multiple forums. 4. Do not post a new topic or question on someone else's thread, start a new thread! 5. Students: Copying code is not the same as learning to design. 6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please). 7. You are not charged extra fees for comments in your code. 8. I am not paid for forum posts. If I write a good post, then I have been good for nothing. |
|
|
|
eteam00写道:
我们没有开始使用巨型FPGA。 不能代表你说话,但Xilinx / ATT 3090a对我来说似乎相当巨大 - 特别是与3030a相比。 35页的OrCad(DOS)原理图。 我的前20个左右的FPGA设计基于3030a和3090a。 我使用了我可以拿到的最大包装:208针四角平板。 我想我的意思是:我没有开始学习使用巨型FPGA进行数字电路设计。 我开始学习带有单独门和触发器的数字电路设计,以及基本的74xx系列逻辑。 ----------------------------是的,我这样做是为了谋生。 以上来自于谷歌翻译 以下为原文 eteam00 wrote: I suppose what I mean was this: I didn't start learning to do digital circuit design with giant FPGAs. I started learning digital circuit design with individual gates and flip-flops, yr basic 74xx-series logic. ----------------------------Yes, I do this for a living. |
|
|
|
我想我的意思是:我没有开始学习使用巨型FPGA进行数字电路设计。
我开始学习带有单独门和触发器的数字电路设计,以及基本的74xx系列逻辑。 我们是恐龙,你和我。 - 鲍勃埃尔金德 签名:新手的自述文件在这里:http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结:1。 阅读手册或用户指南。 你读过手册了吗? 你能找到手册吗?2。 搜索论坛(并搜索网页)以寻找类似的主题。 不要在多个论坛上发布相同的问题。 不要在别人的主题上发布新主题或问题,开始新的主题!5。 学生:复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。 提供有用的详细信息(请与网页,数据表链接).7。 您的代码中的评论不需要支付额外费用。 我没有支付论坛帖子的费用。 如果我写一篇好文章,那么我一无所获。 以上来自于谷歌翻译 以下为原文 I suppose what I mean was this: I didn't start learning to do digital circuit design with giant FPGAs. I started learning digital circuit design with individual gates and flip-flops, yr basic 74xx-series logic. We are dinosaurs, you and I. -- Bob Elkind SIGNATURE: README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369 Summary: 1. Read the manual or user guide. Have you read the manual? Can you find the manual? 2. Search the forums (and search the web) for similar topics. 3. Do not post the same question on multiple forums. 4. Do not post a new topic or question on someone else's thread, start a new thread! 5. Students: Copying code is not the same as learning to design. 6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please). 7. You are not charged extra fees for comments in your code. 8. I am not paid for forum posts. If I write a good post, then I have been good for nothing. |
|
|
|
eteam00写道:
我想我的意思是:我没有开始学习使用巨型FPGA进行数字电路设计。 我开始学习带有单独门和触发器的数字电路设计,以及基本的74xx系列逻辑。 我们是恐龙,你和我。 - 鲍勃埃尔金德 看起来我们有很多人。 就我而言,4000B系列CMOS - 作为ASIC仿真器...... ------------------------------------------“如果它不起作用 模拟,它不会在板上工作。“ 以上来自于谷歌翻译 以下为原文 eteam00 wrote:There are plenty of us about, it would seem. In my case, 4000B series CMOS - as an ASIC emulator... ------------------------------------------ "If it don't work in simulation, it won't work on the board." |
|
|
|
“这是适当的广泛和模糊的答案” - 这正是我所需要的,谢谢你。
“你必须是数字电路设计的新手。” - 我通常是电子和数字系统的自学者(甚至没有提到FPGA),花费我的一部分空闲时间,所以是的,我是数字电路设计的新手。 祝你今天愉快, Ignas 以上来自于谷歌翻译 以下为原文 „here is the appropriate broad and vague answer“ - it is just what I needed, thanks for that. "You must be new to digital circuit design." - I'm a self learner of electronics and digital systems generally (not even mentioning FPGA), spend part of my free time for it, so yes, I am new to digital circuit design. Have a nice day, Ignas |
|
|
|
只有小组成员才能发言,加入小组>>
2322 浏览 7 评论
2734 浏览 4 评论
Spartan 3-AN时钟和VHDL让ISE合成时出现错误该怎么办?
2219 浏览 9 评论
3297 浏览 0 评论
如何在RTL或xilinx spartan fpga的约束文件中插入1.56ns延迟缓冲区?
2369 浏览 15 评论
有输入,但是LVDS_25的FPGA内部接收不到数据,为什么?
658浏览 1评论
请问vc707的电源线是如何连接的,我这边可能出现了缺失元件的情况导致无法供电
465浏览 1评论
求一块XILINX开发板KC705,VC707,KC105和KCU1500
230浏览 1评论
671浏览 0评论
1866浏览 0评论
小黑屋| 手机版| Archiver| 电子发烧友 ( 湘ICP备2023018690号 )
GMT+8, 2024-10-3 01:18 , Processed in 1.165643 second(s), Total 70, Slave 61 queries .
Powered by 电子发烧友网
© 2015 bbs.elecfans.com
关注我们的微信
下载发烧友APP
电子发烧友观察
版权所有 © 湖南华秋数字科技有限公司
电子发烧友 (电路图) 湘公网安备 43011202000918 号 电信与信息服务业务经营许可证:合字B2-20210191 工商网监 湘ICP备2023018690号