模块传播延迟怎么在Spartan 3板上实现

我正在考虑使用板载50 MHz时钟的定时器，但现在我想知道如何在verilog中访问该时钟？
而我假设1 / 50MHz = 20ns是我能得到的最短延迟？



以下为原文

I'm thinking of just using a timer from the on board 50 MHz clock, but now I'm wondering how can I access that clock in verilog? And I'm assuming 1/50MHz = 20ns is the shortest delay I can get?

你好
抱歉，不知道verilog，我们在这里说其他语言，
但
您无法将延迟合成到硅片中。
如果你想到硅必须做什么，它将是一串具有固定延迟的门。
你需要同步思考，事情发生或因为时钟。
Xilinx FPGA具有各种DLL和PLL选项，具体取决于器件，可用于制作更快的内部时钟。
你也可以，如果你小心使用clcok的上升沿和下降沿，或者甚至是时钟的移位来获得更快的电路。
至于如何访问计时器。
当您进行计时器时，它将有一个计数寄存器，您可以访问它。
我可以建议你从几个在线教程开始，他们可能会打破你这种想法。



以下为原文

Hi
 
sorry dont know verilog, we speak the other language over here, 
 
but
 
You can not synthesise a delay into silicon. If you think of what the silicon would have to do, it would be a string of gates with a fixed delay.
 
You need to think syncronously, things happen on or because of a clock.
 
The Xilinx FPGA's have various DLL and PLL options, dependent upon the device , usefull amongst other things for making a faster internal clock.
 
You can also, if you are careful use both the rising and falling edge of a clcok, or even pahse shifts of a clock to get aparantly faster circuits. 
 
As for how to acces the timer.
 
When you make the timer, it will have a counting register, you access that.
 
Can I suggest you start with a few on line tutorials, they might break you in tho this sort of thinking.
 
 

VHDL或Verilog中的延迟结构不能合成到硅中，它们仅用于模拟目的。
如果您的时钟频率为50 MHz（20ns），那么您添加的每个寄存器阶段都会将信号延迟1个时钟周期（20nS）。
------您是否尝试在Google中输入问题？
如果没有，你应该在发布之前。太多结果？
尝试添加网站：www.xilinx.com



以下为原文

Delay constructs in either VHDL or Verilog are not synthesizable into silicon they are intended for simulation purposes only.
 
If you have a clock that is 50 MHz (20ns) then you every register stage that is added will delay the signal by 1 clock period (20nS).
------Have you tried typing your question into Google?  If not you should before posting.
Too many results?  Try adding site:www.xilinx.com