如何在FPGA中实现选定信号的准确延迟

您可以尝试将KEEP约束添加到代码中以防止优化，或者您可以
实例化LUT原语（只需打开库指南即可找到一个简单的原语）。
该
关于实例化原语的好处是你可以通过实例轻松找到它们
您将不可避免地需要的手部位置的名称，以便生成
相对固定的时间结果。
为了更好地控制时间，你可以玩
在FPGA编辑器中使用手动路由进行路由，然后导出定向
路由约束，以便您可以重建设计并具有相同的路径
每次延误。
如果你想微调延迟，你可以有一个链
LUT排列成一系列多路复用器，每个多路复用器选择输出
先前的MUX或原始输入信号。
这将改变数量
LUT信号通过，具体取决于多路复用器的选择输入。
然而，只要意识到路由延迟很重要，所以你仍然需要提交
放置这些多路复用器以获得任何可用的结果。
比较精细的调整
LUT你可以使用进位链，也可以是多路复用（看看图​​书馆
指南，我认为它被称为MUXCY）。
然而，通过这些延迟是非常小的
你真的需要限制路由以防止路由延迟
从完全掩盖变量进位链延迟。
有一个应用笔记
对于Virtex E（类似于Spartan 2的架构），显示了carry的使用
链作为可变延迟元件。
但是，如果您不需要此分辨率的计时
你可能最好坚持使用LUT。
-  Gabor
-  Gabor
在原帖中查看解决方案



以下为原文

You can try to add KEEP constraints to your code to prevent optimizations, or you can
instantiate LUT primitives (just open the libraries guide to find a simple one).  The
nice thing about instantiated primitives is that you can easily find them by instance
name for the hand placement that you will invariably need in order to generate a
relatively fixed timing outcome.  For even more control over timing you can play
with the routing using manual route in the FPGA editor and then export the directed
routing constraints so you can rebuild the design and have the same route
delays each time.  If you want to fine tune the delay you can have a chain of
LUTs arranged as a series of multiplexers, each selecting either the output of
the previous MUX or the original input signal.  This will change the number of
LUTs the signal travels through depending on the select inputs to the muxes.
Just realize however that routing delays are significant, so you still need to hand
place these muxes to get any kind of usable results.  For finer tuning than
LUTs you can use carry chains, which can also be muxes (look in the Libraries
Guide, I think it's called MUXCY).  However the delay through these is quite small
and you will REALLY need to restrict the routing to prevent the route delays
from totally overshadowing the variable carry chain delays.  There was an app note
for Virtex E (similar in architecture to Spartan 2) that shows the use of carry
chains as a variable delay element.  If you don't need this resolution of timing, however
you may be best to stick with LUTs.
 
-- Gabor
-- GaborView solution in original post

让 - 马克，
我相信会有一个简单的解决方案来解决你的问题。
但是，我很难理解您对问题的描述。
你能重新说出你的描述吗？
请包括描述三种信号及其生成方式的详细信息以及它们之间的时序关系。
它们都是以共同的时钟频率生成的，还是每个都来自一个单独的时基？
请描述FPGA时基，以及FPGA时基是否与产生三个输入信号的时基（或时基）相关。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

Jean-Marc,
 
I believe there will be a straightforward solution to your problem.  However, I have difficulty understanding your description of your problem.  Would you please re-phrase your description?
 
Please include details which describe the three signals and how they are generated and their timing relationship with respect to each other.  Are they all generated with a common clock frequency, or do they each come from a separate timebase?
 
Please describe the FPGA timebase, and if the FPGA timebase is related to the timebase (or timebases) which generate the three input signals.
 
- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

我看到一些问题：
Spartan 2没有任何IODELAY元素，比如只插入一个更新的系列
校准延迟。
Spartan 2具有DLL，它只能从输入时钟生成4个相位，但如果你
不要同步运行一个constate rate clock（不是你的变量引用）
是没用的。
您可以使用不同的IO标准，驱动器和转换速率来改变它们
输出延迟，但这个范围最多只有几纳秒。
因此，看起来你会因为一些不太准确的延迟而陷入困境
像LUT或可能携带链的元素。
你需要找到一种方法
校准这些延迟以使它们有用。
对于单个输出，是否有一些原因您不想使用外部
设备为你生成延迟？
-  Gabor
-  Gabor



以下为原文

Some issues I see:
 
Spartan 2 does not have any IODELAY elements like newer series that just insert a
calibrated delay.
 
Spartan 2 has DLL's that can generate only 4 phases from an input clock, but if you
do not run synchronously to a constate rate clock (not your variable reference) this
is of no use.
 
You can play around with different IO standards, drives, and slew rates to get different
output delays, but the range on this is in the handful of nanoseconds at best.
 
So it looks like you're stuck with making your delay with some not very accurate
elements like LUTs or possibly carry-chains.  You would need to find a way to
calibrate these delays to make them useful.
 
For a single output, is there some reason you don't want to use an external
device to generate the delay for you?
 
-- Gabor
-- Gabor

eteam，
感谢您的快速回答，对不起，如果我的描述不清楚！
第二次尝试：smileywink：
FPGA输入：可编程时钟（几KHz至20MHz，不是恒定频率）
FPGA输出：在同一输入时钟上产生3个不同的信号
2个输出信号在外部组件中具有传播延迟路径，而1个没有。
3个信号需要在接收器处同相到达。
所以我要延迟提前到达的信号，以保持所有信号同相。
gszakacs
IODELAY：是的，当我搜索解决方案时，我看到了这个，但我找不到SPARTAN 2
DLL：不是恒定频率，需要低至几KHz => DLL范围之外
IO参数：我需要很多ns，我同意，这还不够
自己做出延迟：如果这是唯一的解决方案，我会接受准确性的损失。
你有延迟组件的例子吗？
我试过，但似乎优化删除我的组件（我看到范围没有变化）。
我无法使用外部设备产生延迟，因此无法在板上进行修改（已经工业化）
感谢您的支持 ！



以下为原文

eteam,
 
Thanks for your quick answer, and sorry if my description isn't clear !
Second try :smileywink:
FPGA input : programmable clock (few KHz up to 20MHz, not a constant frequency)
FPGA outputs: 3 differents signals generated with process on the same input clock
2 of the outputs signals have propagation delay path in externals components, and 1 hasn't.
The 3 signals need to arrive in phase at the receiver.
So I've to delay the signal which arrive in advance to keep all signals in phase.
 
 
gszakacs
IODELAY : Yes I see this when I search solution but I find nothing for SPARTAN 2
DLL : not a constant frequency and need down to few KHz => outside DLL range
IO parameters : I need to many ns, I agree, it'll not enough
Own make delay : if it's the only solution, I'll accept the loss in accuracy. Do you have an example of delay component ? I tried but it seems that optimisation remove my component (I see no change on scope).
I can't use an external device to generate the delay, cause modification on board is impossible (already industrialized)
 
 
Thanks for your support !
 
 
 
 

看看我是否正确理解了您的问题。
这是您的框图：
您的问题是补偿FPGA内部固定的板载延迟DELAY1和DELAY2。
它是否正确？
FPGA内部还有另一个可用的时钟，也许是一个固定频率的时钟？
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

See if I understand your problem correctly.  Here's your block diagram:

Your problem is to compensate for fixed on-board delays DELAY1 and DELAY2 inside the FPGA.
 
Is this correct?
 
Is there another clock available inside the FPGA, perhaps one that is fixed frequency?
 
- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

您可以尝试将KEEP约束添加到代码中以防止优化，或者您可以
实例化LUT原语（只需打开库指南即可找到一个简单的原语）。
该
关于实例化原语的好处是你可以通过实例轻松找到它们
您将不可避免地需要的手部位置的名称，以便生成
相对固定的时间结果。
为了更好地控制时间，你可以玩
在FPGA编辑器中使用手动路由进行路由，然后导出定向
路由约束，以便您可以重建设计并具有相同的路径
每次延误。
如果你想微调延迟，你可以有一个链
LUT排列成一系列多路复用器，每个多路复用器选择输出
先前的MUX或原始输入信号。
这将改变数量
LUT信号通过，具体取决于多路复用器的选择输入。
然而，只要意识到路由延迟很重要，所以你仍然需要提交
放置这些多路复用器以获得任何可用的结果。
比较精细的调整
LUT你可以使用进位链，也可以是多路复用（看看图​​书馆
指南，我认为它被称为MUXCY）。
然而，通过这些延迟是非常小的
你真的需要限制路由以防止路由延迟
从完全掩盖变量进位链延迟。
有一个应用笔记
对于Virtex E（类似于Spartan 2的架构），显示了carry的使用
链作为可变延迟元件。
但是，如果您不需要此分辨率的计时
你可能最好坚持使用LUT。
-  Gabor
-  Gabor



以下为原文

You can try to add KEEP constraints to your code to prevent optimizations, or you can
instantiate LUT primitives (just open the libraries guide to find a simple one).  The
nice thing about instantiated primitives is that you can easily find them by instance
name for the hand placement that you will invariably need in order to generate a
relatively fixed timing outcome.  For even more control over timing you can play
with the routing using manual route in the FPGA editor and then export the directed
routing constraints so you can rebuild the design and have the same route
delays each time.  If you want to fine tune the delay you can have a chain of
LUTs arranged as a series of multiplexers, each selecting either the output of
the previous MUX or the original input signal.  This will change the number of
LUTs the signal travels through depending on the select inputs to the muxes.
Just realize however that routing delays are significant, so you still need to hand
place these muxes to get any kind of usable results.  For finer tuning than
LUTs you can use carry chains, which can also be muxes (look in the Libraries
Guide, I think it's called MUXCY).  However the delay through these is quite small
and you will REALLY need to restrict the routing to prevent the route delays
from totally overshadowing the variable carry chain delays.  There was an app note
for Virtex E (similar in architecture to Spartan 2) that shows the use of carry
chains as a variable delay element.  If you don't need this resolution of timing, however
you may be best to stick with LUTs.
 
-- Gabor
-- Gabor

嗨，大家好，
谢谢你的回答，抱歉延误，我不在办公室！
BOB：您的框图和问题描述是正确的！
是的，FPGA中还有一个时钟，一个固定的时钟：40MHz。
Gabor：本周我很忙，我会尽快尝试！
非常感谢您的支持 ！



以下为原文

Hi guys,
 
Thanks for your answer and sorry for the delay, I was out of office !
 
BOB : your block diagram and problem description is correct ! And yes, there is an other clock in the FPGA, a fixed one : 40MHz.
 
Gabor : I'm pretty busy this week, I'll try it asap !
 
 
Many thanks for your support !
 
 

使用40MHz时钟，您可以通过使用40MHz时钟的两个边沿以大约12.5nS的增量添加内部延迟。
输出延迟调整的粒度是否足够精细？
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

With a 40MHz clock, you can add internal delay in roughly 12.5nS increments by using both edges of the 40MHz clock.  Is that fine enough granularity for output delay adjustment?
 
- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

鲍勃，
我需要大约20ns的延迟！
也许40MHz x 2将有助于获得更多粒度：6.25ns x 3 = 18.75ns（而不是25ns）
你能解释一下我怎么能用这个时钟来建立这个延迟？
谢谢



以下为原文

Bob,
 
I need approximately 20ns delay ! Maybe 40MHz x 2 will help to get more granularity : 6.25ns x 3 = 18.75ns (instead of 25ns)
Could you explain how can I build this delay with this clock ?
 
Thanks

在40MHz时钟（25nS周期）下，您可以在电路板上的目标接收器上将所有三个输出在彼此的25nS内。
您只需在两个输出的输出路径中插入足够的流水线延迟寄存器，并将电路板延迟最小化到目标接收器即可。
这有意义吗？
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
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以下为原文

At 40MHz clock (25nS period), you can get all three outputs to within 25nS of each other at the destination receiver on the board.
 
You do this simply by inserting enough pipeline delay registers in the output paths of the two outputs with the least circuit board delay to the destination receiver.
 
Does this make sense?
 
- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

使用LUT和“保持”约束修复问题。
我使用示波器校准了延迟（串行LUT的数量）并获得了可接受的精度！
非常感谢Bob＆amp;
Gabor求助！
：smileywink：



以下为原文

Problem fixed using LUT and "keep" constraint.
I calibrated the delay (number of serial LUT) using scope and got acceptable accuracy !
 
Many thanks to Bob & Gabor for your help !
:smileywink:

使用LUT和“保持”约束修复问题。
我使用示波器校准了延迟（串行LUT的数量）并获得了可接受的精度！
您不关心过程，温度和电压因素是一件好事。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
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以下为原文

Problem fixed using LUT and "keep" constraint.
I calibrated the delay (number of serial LUT) using scope and got acceptable accuracy !

It's a good thing you aren't concerned about process, temperature, and voltage considerations.
 
- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.