在Simulation中没有看到信号传播的延迟

你好
我的项目采用斯巴达3A XC3S200AFPGA，我正在经历一段艰难时期。
发生的事情是该项目在仿真（ISIM）中完美运行，但是当编程fpga时，结果并不完全是期望的。工作一段时间然后完全阻塞。
我怀疑在Simulation中没有看到信号传播的延迟，但是我没有工具可以实时调试。
我走在正确的轨道上？
是否有任何文档或教程来检查此问题？
我认为问题在于编程代码。
我应该考虑什么样的信号进行审核？
我有信号在状态机的各个阶段生成，然后用作计数器的RST或EC，FSM和计数器的时钟相同。
这些信号被认为是异步还是同步？
PS：我正在使用Xula200模块和ISE Design Suit 14.3



以下为原文

Hi
I am experiencing bad times with my project with a spartan 3A XC3S200A fpga. What happens is that the project works perfectly in simulation (ISIM) but when programming the fpga  the result is not entirely expected.
Works for a while and then completely blocks. I'm suspicious that exist delays in the propagation of signals which are not seen in Simulation, but I don´t have the tools to do debugg in real time.

I'm on the right track? Is there any documentation or tutorial to check this problem?

I think the problem is the programmed code. What kind of signals should I consider for review?

I have signals that are being generated in various stages of state machines and then used as RSTs or ECs for counters and the clock is the same for both FSM and Counters. These signals are considered to be asynchronous or synchronous?

PS: I'm using a Xula200 module and ISE Design Suit 14.3