如何摆脱设置时违规警告

你好论坛
我建立了一个DMX合并与PSoC5LP套件（3 DMX输入和1 DMX输出）。
现在我想把时钟设置得和物理允许的一样快。
但是我得到一个警告：警告-1366：从时钟（CyBuxCLK）到时钟（CcLogi1）的路径中发现设置时间违反。
我能得到的最好的表现是什么？
格恩特
静态时序分析项目：PSoC5测试建立时间：12/28／17 18:54∶54设备：CY8C588Lti-LP097温度：0C-5125C VDDA：5 VDDABUF：5 VDDD：5 VDDIO0:5 VDDIO1: 5 VDIO2: 5 VDIO3：5 VUSB：5电压：5扩展所有崩溃所有显示路径隐藏所有路径
定时违反部分
注意：如果您的设计只在典型的房间温度下运行，那么在系统DWR中为您的应用选择较窄的温度范围有助于工具找到符合时序的路由解决方案。
ViolationSource ClockDestination ClockSlack（NS）设置CyBuffCl CKCROLY1-1-7.508-时钟摘要部分
ClockDomainNominal FrequencyRequired FrequencyMaximum频率为100.kHZ1.000 kHz N/A CyimyCyoMo0.000 MHZ8000 MHz N/A CysMycCycCythMythCK80.000 MHZ80.000 MHz N/A CyBuxCykCyrasMyCLK80.000 MHZ80.000 MHZ49980 MHZQueCuthyCyCordMaLCK4.000 MHZ4.000 MHZ43.435 MHZCYPLLO OXCPLPLLL OU8000 000 MHZ80.000兆赫N/A CyxTalyCyxTal8000 MHZ8000兆赫N/A
PSOC5Test.Zip
5.2兆字节



     以下为原文
  Hello Forum,

i built an DMX-Merger with the PSOC5LP Kit (3 DMX Inputs and 1 DMX Output).
Now i want to setup the clocks as fast as physics allow.

But i get a warning: Warning-1366: Setup time violation found in a path from clock ( CyBUS_CLK ) to clock ( Clock_1 ).

What is the best performance that i can get?

Günter

Static Timing Analysis

Project :	Psoc5test
Build Time :	12/28/17 18:54:54
Device :	CY8C5888LTI-LP097
Temperature :	0C - 85/125C
VDDA :	5.00
VDDABUF :	5.00
VDDD :	5.00
VDDIO0 :	5.00
VDDIO1 :	5.00
VDDIO2 :	5.00
VDDIO3 :	5.00
VUSB :	5.00
Voltage :	5.0

Expand All | Collapse All | Show All Paths | Hide All Paths

- Timing Violation Section  

Note: If your design will only ever run at typical room temperatures, selecting the narrower temperature range in the system DWR for your application helps the tool to find timing-compliant routing solutions.
[tr]ViolationSource ClockDestination ClockSlack(ns)[/tr]

Setup
	CyBUS_CLK	Clock_1	-7.508

- Clock Summary Section
[tr]ClockDomainNominal FrequencyRequired FrequencyMaximum FrequencyViolation[/tr]

CyILO	CyILO	1.000 kHz	1.000 kHz	N/A
CyIMO	CyIMO	8.000 MHz	8.000 MHz	N/A
CyMASTER_CLK	CyMASTER_CLK	80.000 MHz	80.000 MHz	N/A
CyBUS_CLK	CyMASTER_CLK	80.000 MHz	80.000 MHz	49.980 MHz	Frequency
Clock_1	CyMASTER_CLK	4.000 MHz	4.000 MHz	43.435 MHz
CyPLL_OUT	CyPLL_OUT	80.000 MHz	80.000 MHz	N/A
CyXTAL	CyXTAL	8.000 MHz	8.000 MHz	N/A

•   Psoc5test.zip 5.2 MB