Vivado会对内存级联中未连接的奇偶校验信号发出很多警告

大家好，
我在Vivado中为您的FPGA合成处理器及其存储器。
在写入（然后读取）内存时，我在此处理器上执行程序时遇到问题。
存储器由Verilog RTL合成为BRAM，具有位写使能。程序指令序列与模拟不同（可能从存储器读取错误值）。
在设计实现期间，Vivado会对内存级联中未连接的奇偶校验信号发出很多警告，请参见下文：
警告：[DRC 23-20]规则违规（REQP-1902）RAMB36E2_AB_cascade_out_must_use_parity  -  RAMB36E2单元格i_core / sram_block_all [0] .i_l2sram / sram_block.genblk1 [0] .i_mem / mem_core_reg_bram_0使用CASDOUTA将CASCADE_ORDER_A属性设置为FIRST [31
：0]总线使用，但缺少CASDOUTPA [3：0]总线的连接。
警告：[DRC 23-20]规则违规（REQP-1902）RAMB36E2_AB_cascade_out_must_use_parity  -  RAMB36E2单元格i_core / sram_block_all [0] .i_l2sram / sram_block.genblk1 [0] .i_mem / mem_core_reg_bram_1将CASCADE_ORDER_A属性设置为带有CASDOUTA的MIDDLE [31
：0]总线使用，但缺少CASDOUTPA [3：0]总线的连接。
我在Xilinx文档中找不到有关此DRC警告的相关信息。
在不使用奇偶校验时，此警告是否会导致潜在问题？
问候，
麦克风



以下为原文

Hi all,
I synthesize processor and its memories in Vivado for your FPGA. I have issue during program execution on this processor when writing (and then reading) to memory occurs. The memories are synthesized from Verilog RTL as BRAM with bit write enable. The program instruction sequence is different than in simulation (probably wrong value is read from the memories). During the design implementation Vivado produces a lot of warning about unconnected parity signals in the memory cascade, see below: WARNING: [DRC 23-20] Rule violation (REQP-1902) RAMB36E2_AB_cascade_out_must_use_parity - The RAMB36E2 cell i_core/sram_block_all[0].i_l2sram/sram_block.genblk1[0].i_mem/mem_core_reg_bram_0 has CASCADE_ORDER_A attribute set to FIRST with the CASDOUTA[31:0] bus used, but is missing connection(s) for the CASDOUTPA[3:0] bus.WARNING: [DRC 23-20] Rule violation (REQP-1902) RAMB36E2_AB_cascade_out_must_use_parity - The RAMB36E2 cell i_core/sram_block_all[0].i_l2sram/sram_block.genblk1[0].i_mem/mem_core_reg_bram_1 has CASCADE_ORDER_A attribute set to MIDDLE with the CASDOUTA[31:0] bus used, but is missing connection(s) for the CASDOUTPA[3:0] bus.I cannot find relevant information on this DRC warning in Xilinx documentation. May this warning cause potential problems when not using parity checking? Regards,Mike