不能在不同时钟区域锁定负载的情况下路由

大家好，
我收到以下错误，请让我知道解决方案。
工具：ISE 14.6
设备：virtex 6
错误：位置：1377  - 区域时钟网络“u_ddr3 / u_memc_ui_top / u_mem_intfc / phy_top0 / clk_rsync”不能在不同时钟区域锁定负载的情况下路由，因此源不可能路由到所有负载。
请参阅下面的每个时钟区域中的示例锁定组件列表。
有关时钟区域规则的更多信息，请参阅体系结构用户指南。
要使用部分路由设计调试您的设计，请允许mapper / placer完成执行（通过将环境变量XIL_PAR_DEBUG_IOCLKPLACER设置为1）。
错误：位置：1377  - 区域时钟网络“u_ddr3 / u_memc_ui_top / u_mem_intfc / phy_top0 / clk_rsync”不能在不同时钟区域锁定负载的情况下路由，因此源不可能路由到所有负载。
请参阅下面的每个时钟区域中的示例锁定组件列表。
有关时钟区域规则的更多信息，请参阅体系结构用户指南。
要使用部分路由设计调试您的设计，请允许mapper / placer完成执行（通过将环境变量XIL_PAR_DEBUG_IOCLKPLACER设置为1）。
谢谢娜文G K.



以下为原文

Hi all,


I am getting the below error, please let me know the solution.
Tool: ISE 14.6
Device: virtex 6


ERROR:Place:1377 - Regional clock net
   "u_ddr3/u_memc_ui_top/u_mem_intfc/phy_top0/clk_rsync<0>" is not routable with
   loads locked in different clock regions such that it will be impossible for
   the source to be routed to all loads. See below for a list of sample locked
   components in each clock region. For more information on the clock region
   rules, please refer to the architecture user's guide. To debug your design
   with partially routed design, please allow mapper/placer to finish the
   execution (by setting environment variable XIL_PAR_DEBUG_IOCLKPLACER to 1).
   
ERROR:Place:1377 - Regional clock net
   "u_ddr3/u_memc_ui_top/u_mem_intfc/phy_top0/clk_rsync<0>" is not routable with
   loads locked in different clock regions such that it will be impossible for
   the source to be routed to all loads. See below for a list of sample locked
   components in each clock region. For more information on the clock region
   rules, please refer to the architecture user's guide. To debug your design
   with partially routed design, please allow mapper/placer to finish the
   execution (by setting environment variable XIL_PAR_DEBUG_IOCLKPLACER to 1).
  
Thanks
Naveen G K