获取错误：地点：905由区域时钟网驱动的组件

嗨，
您使用的是什么版本的ISE版本？
您可以使用变量“XIL_PAR_DEBUG_IOCLKPLACER to 1”并尝试检查设计中元素的位置吗？
问候，
Achutha
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以下为原文

Hi,
 
What version of ISE version you are using?
 
Can you use the variable  "XIL_PAR_DEBUG_IOCLKPLACER to 1" and try to check the placement of the elements in the design?
 
Regards,
Achutha
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我使用的是ISE版本14.7
我试图将该变量设置为1。



以下为原文

i am using ISE version 14.7
 
i am trying to set that variable to 1.

嗨，
检查BUFR是如何驱动的？
它是从IO端口驱动的吗？
如果是，该端口是否锁定时钟IO？
同时启用envoronmental变量并检查放置的设计。
了解负载是如何放置的，它们是否与CCIO的时钟区域位于同一时钟区域。
谢谢，
迪皮卡。
谢谢，迪皮卡.----------------------------------------------
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以下为原文

Hi,
 
Check how is the BUFR driven?
 
Is it driven from IO port? If yes, is this port locked to clock capable IO?
 
Also enable the envoronmental variable and check the placed design. See how the loads are placed, whether they are placed in same clock region as that of the CCIO or not.
 
Thanks,
Deepika.
Thanks,
Deepika.
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嗨，
根据您的观察，错误消息似乎令人困惑。
您使用的是哪个版本的工具？
我建议使用最新的Vivado 2014.2或ISE 14.7。
您也可以尝试删除BUFR约束。
让我们发布运行和更新。
问候
Sikta



以下为原文

Hi,
Based on your observation, the error message seems confusing. Which version of tools are you using?
I would recommend to use the latest one Vivado 2014.2 or ISE 14.7.
 
You can also try by removing the BUFR constraint. Keep us posted with the runs and updates.
 
Regards
Sikta

嗨，您是否尝试过该变量并检查信号的连通性？您能否共享连接片段？问题是否已解决？问候，Achutha
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以下为原文

Hi,
Did you try the variable and check the connectivity of the signal?
Can you share the snippet of connectivity?
Is the issue resolved?
Regards,
Achutha---------------------------------------------------------------------------------------------
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嗨Achutha，
谢谢你的回复。
在我的设计中，使用了10个中的9个MMCM，而BUFGCTRL在我的设计中也更多
工具无法理解MMCM的放置位置，因为几乎所有内核都位于FPGA器件的顶层
我为所有MMCM和BUFGCTRL提供了Area约束
之后我能够实现设计
谢谢



以下为原文

Hi Achutha,
 
Thanks for ur reply.
 
In my design am using 9 MMCMs out of 10.and BUFGCTRLs also more in my design
 
Tool is not able to understand where to place the MMCMs,because almost cores are in top part of the FPGA device
i gave Area constraint for all MMCMs and BUFGCTRLs
 
after that i am able to implement the design
 
Thanks