完善资料让更多小伙伴认识你,还能领取20积分哦, 立即完善>
嗨,
来自Altera Quartus背景后,我是Vivado工具流程的新手。 我正在使用Vivado 2017.2。 我试图弄清楚为什么地点和路线(实施)阶段已经优化了在合成阶段之后仍然存在的一堆逻辑。 我已经在GUI中搜索了实现日志,找到了已消失但未列出任何内容的设计对象的名称。 我在.runs / impl_1文件夹中查找但是日志文件并没有向我跳出来。 指针将不胜感激! 谢谢 以上来自于谷歌翻译 以下为原文 Hi, Im new to the Vivado tool flow after coming from an Altera Quartus background. Im using Vivado 2017.2. Im trying to figure out why the place and route (implementation) stage has optimized away a bunch of logic that is still present after the synthesis stage. Ive searched the implementation log within the GUI for the name of the design object that has disappeared but nothing is listed. Im looking in the .runs/impl_1 folder but a log file isnt jumping out at me. And pointers would be appreciated! Thanks |
|
相关推荐
4个回答
|
|
感谢回复,这帮助了我,虽然日志文件的名称有点奇怪....为什么“runme”..?
谢谢 在原帖中查看解决方案 以上来自于谷歌翻译 以下为原文 Thanks both for the replies, this helped me out, although the name of the log file is a bit odd .... why "runme" .. ? Thanks View solution in original post |
|
|
|
HI @alangford,
在运行文件夹中: .runs / impl_1 / runme.log 或者您还可以看到完整的vivado.log文件,该文件是在您启动vivado的位置生成的(只需在tcl控制台中键入pwd即可知道此位置)。 问候, 弗洛朗 FlorentProduct应用工程师 - Xilinx技术支持EMEA ------------------------------------------ -------------------------------------------------- ----------------------------不要忘记回复,kudo,并接受作为解决方案。 以上来自于谷歌翻译 以下为原文 HI @alangford, In the run folder: .runs/impl_1/runme.log Or you can also see the full vivado.log file which is generated at the location from where you have launched vivado (just type pwd in the tcl console to know this location). Regards, Florent Florent Product Application Engineer - Xilinx Technical Support EMEA ------------------------------------------------------------------------------------------------------------------------ Don't forget to reply, kudo, and accept as solution. |
|
|
|
@alangford,
在“实施”设置中,将“-verbose”开关设置为更多选项,如下所示,为每个实现阶段启用或默认启用(opt_design,place_design,route_design)以获取详细报告。 设置开关后,您将在runme.log文件中看到详细报告,该文件将出现在/.runs/impl_1文件夹中。 另请参阅下面的实施用户指南中的第2章,了解完整的Vivado实施流程: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_2/ug904-vivado-implementation.pdf --Syed -------------------------------------------------- -------------------------------------------请注意 - 请标记答案 如果提供的信息有用,请“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢Kudos .------------------------ -------------------------------------------------- ------------------- 以上来自于谷歌翻译 以下为原文 @alangford, In the Implementation setting, set "-verbose" switch in more options as shown below for each implementation stage which is enabled or on by default (opt_design, place_design, route_design) to get the detailed report. Once the switch is set, you will see the detailed report in runme.log file which will be present in Also check Chapter 2 in below Implementation user guide to know the complete Vivado implementation flow: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_2/ug904-vivado-implementation.pdf --Syed --------------------------------------------------------------------------------------------- Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. --------------------------------------------------------------------------------------------- |
|
|
|
感谢回复,这帮助了我,虽然日志文件的名称有点奇怪....为什么“runme”..?
谢谢 以上来自于谷歌翻译 以下为原文 Thanks both for the replies, this helped me out, although the name of the log file is a bit odd .... why "runme" .. ? Thanks |
|
|
|
只有小组成员才能发言,加入小组>>
2415 浏览 7 评论
2821 浏览 4 评论
Spartan 3-AN时钟和VHDL让ISE合成时出现错误该怎么办?
2292 浏览 9 评论
3372 浏览 0 评论
如何在RTL或xilinx spartan fpga的约束文件中插入1.56ns延迟缓冲区?
2458 浏览 15 评论
有输入,但是LVDS_25的FPGA内部接收不到数据,为什么?
1095浏览 1评论
请问vc707的电源线是如何连接的,我这边可能出现了缺失元件的情况导致无法供电
579浏览 1评论
求一块XILINX开发板KC705,VC707,KC105和KCU1500
441浏览 1评论
2000浏览 0评论
723浏览 0评论
小黑屋| 手机版| Archiver| 电子发烧友 ( 湘ICP备2023018690号 )
GMT+8, 2024-12-20 21:57 , Processed in 1.375192 second(s), Total 85, Slave 68 queries .
Powered by 电子发烧友网
© 2015 bbs.elecfans.com
关注我们的微信
下载发烧友APP
电子发烧友观察
版权所有 © 湖南华秋数字科技有限公司
电子发烧友 (电路图) 湘公网安备 43011202000918 号 电信与信息服务业务经营许可证:合字B2-20210191 工商网监 湘ICP备2023018690号