for always可以在block中合成的吗？

你好@ u4223374
我看到了你的几个帖子
https://forums.xilinx.com/t5/General-Technical-Discussion/is-nested-for-loops-synthesizable/td-p/685820
关于设计FSM。
你能帮我解决我的问题吗？
提前致谢，
沙



以下为原文

Hi @u4223374
 
I saw couple of your posts on 
 
https://forums.xilinx.com/t5/General-Technical-Discussion/is-nested-for-loops-synthesizable/td-p/685820
 
regarding designing FSM. 
 
Can you help me with my problem as well?
 
Thanks in advance,
Sandy
 

@ sandy_1022
哇，现在每个人都想要我！
答案与您链接的主题几乎相同。
您可以使用循环，但综合工具将构建整个循环以同时运行。
如果您正在进行3 * 3矩阵乘法，那么这将占用27个DSP片 - 这可能正是您想要的，并且可以节省写出长而错误的27行代码。
如果您正在进行64 * 64矩阵乘法，那么这将占用262,144个DSP片（即22个最大的Virtex Ultrascale +芯片） - 这很可能不是您所追求的。
实际上，对于任何超过3 * 3矩阵的东西，您可能需要实现一个FSM，每个时钟周期（例如）一个输出元素。
这将每个周期的工作从n³减少到n  - 因此64 * 64矩阵只需要64个DSP片（但它需要64 * 64 = 4096个时钟周期）。
当然，FSM意味着您可以即时更改矩阵大小，而使用for循环，任何大小更改都需要重新运行合成和实现。



以下为原文

@sandy_1022
 
Wow, everyone wants me now!
 
The answer is pretty much the same as in the thread you linked. You can use a loop, but the synthesis tool will build the entire loop to run simultaneously.
 
If you're doing 3*3 matrix multiplication, then this will occupy 27 DSP slices - which may well be exactly what you want, and saves writing out 27 long, mistake-prone lines of code.
 
If you're doing 64*64 matrix multiplication, then this will occupy 262,144 DSP slices (ie 22 of the largest Virtex Ultrascale+ chips) - which is most likely not what you're after.
 
 
Realistically, for anything over a 3*3 matrix you probably need to implement a FSM that does (for example) one output element per clock cycle. This reduces the work per cycle from n³ to n - so a 64*64 matrix will only need 64 DSP slices (but it'll take 64*64 = 4096 clock cycles). And, of course, a FSM means that you can change the matrix size on-the-fly, whereas with the for-loop any size changes require synthesis and implementation to be re-run.

嗨@ u4223374，
感谢您的答复。
我已经使用case语句将我的整个“for循环”转换为FSM。
我的下一个问题是，我可以将我的“for loop”变量等同于FSM中的零吗？
如果我的for循环是for（m = 0; m因为我有多个“for循环”并再次使用相同的变量，我必须将它等于零，以便我可以使用相同的变量
循环不同。
再次感谢，
沙



以下为原文

Hi @u4223374,
 
Thanks for your response. I have converted my entire "for loops" into an FSM using case statements. 
 
My Next question is , Can i equate my "for loop" variable to zero inside the FSM? Something like "m<=4'b0000" if my for loop is for(m=0;m<4;m=m+1) because i have multiple "for loops" and to use the same variable again, i have to equate it to zero so that i can use the same variable for a different for loop.
 
Thanks again,
Sandy

@ sandy_1022
你能发一个代码的例子吗？
您当然可以在FSM内将值重置为零，以便再次使用它。
例如，在2D循环中，这样的工作正常：
reg [3：0] m = 4'b0;
reg [3：0] n = 4'b0;
reg done = 1'b0;
总是@（posedge clk）开始
如果（〜完成）开始
如果（m
唯一的限制是你只能在一个区块中设置它;
如果你在其他地方设置m，它也不能在FSM中设置。



以下为原文

@sandy_1022
 
Could you post an example of the code?
 
You can certainly reset a value back to zero inside the FSM so you can use it again. For example, in a 2D loop something like this works fine:
 
reg [3:0] m = 4'b0;reg [3:0] n = 4'b0;reg done = 1'b0;always @(posedge clk) beginif (~done) beginif (m < 4) beginm <= m + 1'b1;end else if (m < 4) beginm <= 1'b0;n <= n + 1'b1;end else beginm <= 1'b0;n <= 1'b0;done <= 1'b1;endendendThe only limitation is that you can only set it in one block; if you're setting m somewhere else, it cannot be set in the FSM too.

喜@ u4223374，
你的帖子非常有帮助。
非常感谢
谢谢，
沙



以下为原文

hi @u4223374,
 
Your post was very helpful. Thank you so much
 
Thanks,
Sandy