vhdl中的哪个子句可以合成

weilings写道：
如你所知，XST无法合成'等待20 ns'，我想知道的是：是否有任何其他的XST无法合成？
哦好的。
现在我们明白了。
XST手册实际上详细介绍了可合成的内容和内容。
----------------------------是的，我这样做是为了谋生。
在原帖中查看解决方案



以下为原文

weilings wrote:
As you know the 'wait for 20 ns' can not be synthesized by XST, what i want to know is: is there anyothers that can't be synthesized by XST?

Oh, ok. NOW we understand.
 
The XST manual actually goes into some detail about what is, and what is not, synthesizable.
----------------------------Yes, I do this for a living.View solution in original post

嗨，
您是否参考过http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/xst_v6s6.pdf的第3章
谢谢，
迪皮卡。
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Hi,
 
Did you refer to chapter-3 of http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_6/xst_v6s6.pdf
 
Thanks,
Deepika.
Thanks,
Deepika.
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我没有找到关于综合条款的任何线索，我不知道我是否遗漏了你发给我的pdf中的内容。



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I didn't find any clue about the synthesis clause, I don't know whether I miss something in the pdf you send to me.

weilings写道：
我没有找到关于综合条款的任何线索，我不知道我是否遗漏了你发给我的pdf中的内容。
你在说什么条款？
当你说“综合条款”时，我们不知道你的意思。
我从来没有听过这个词，有些头发是灰色的。
----------------------------是的，我这样做是为了谋生。



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weilings wrote:
I didn't find any clue about the synthesis clause, I don't know whether I miss something in the pdf you send to me.

What clause are you talking about?
 
We have no idea what you mean when you say "synthesis clause." I've never heard that term, and some of my hair is gray.
----------------------------Yes, I do this for a living.

我的意思是可以在ISE中合成的条款。
我不知道自己是否足够清楚。



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I mean the clause that can be synthezised in ISE. I don't know whether I made myself clear enough.

weilings写道：
我的意思是可以在ISE中合成的条款。
我不知道自己是否足够清楚。
你显然是非常的。
请在此上下文中定义“Clause”。
----------------------------是的，我这样做是为了谋生。



以下为原文

weilings wrote:
I mean the clause that can be synthezised in ISE. I don't know whether I made myself clear enough.

You are remarkably UNCLEAR. 
 
Please define "Clause," as used in this context.
----------------------------Yes, I do this for a living.

如你所知，XST无法合成'等待20 ns'，我想知道的是：是否有任何其他的XST无法合成？



以下为原文

As you know the 'wait for 20 ns' can not be synthesized by XST, what i want to know is: is there anyothers that can't be synthesized by XST?

weilings写道：
如你所知，XST无法合成'等待20 ns'，我想知道的是：是否有任何其他的XST无法合成？
哦好的。
现在我们明白了。
XST手册实际上详细介绍了可合成的内容和内容。
----------------------------是的，我这样做是为了谋生。



以下为原文

weilings wrote:
As you know the 'wait for 20 ns' can not be synthesized by XST, what i want to know is: is there anyothers that can't be synthesized by XST?

Oh, ok. NOW we understand.
 
The XST manual actually goes into some detail about what is, and what is not, synthesizable.
----------------------------Yes, I do this for a living.

嗨，
除了xilinx文档之外，您可能需要查看VHDL的综合标准。
（IEEE 1076.6）
该标准定义了可合成的语句。
所有其他语句都被忽略（例如，之后）或导致像wait for语句之类的错误。
您应该注意到供应商特定的实现有时支持标准未涵盖的功能。
乍一看这些可能很有趣，但是当您需要将代码用于其他工具时会造成麻烦。
文件I / O就是这样的事情。
由于标准不支持的明显原因，XST允许例外以便于初始化ROM。
断言/报告也被忽略。
虽然我建议对同步过程使用“if rising_edge（clock）”语法，因为你也可以在ISE语言模板中找到它，你也可以使用“wait until rising_edge（clock）进行综合。”但这不是你的问题
。）
但即使你以错误的方式使用这些有效的结构，编译器也会给你一个错误信息。
有时因为你编写的代码根据VHDL综合标准没有有效的同步描述，有时因为硬件无法实现它（例如双边FF）。
有一个很好的综合 
Eilert



以下为原文

Hi,
aside from the xilinx documentation you might want to take a look at the synthesis standard for VHDL.
(IEEE 1076.6)
This standard defines what statements are synthesizable.
All other statements are either ignored (e.g. after) or lead to errors like the wait for statement.
 
You should notice that vendor specific implementations sometimes support features, not covered by the standard.
These might be interesting at first glance, but cause trouble when you need to use your code with another tool.
File I/O is such a thing.
For obvious reasons not supported by the standard, XST allows an exception for convenient initializing of ROMs.
 
assertion/report is also ignored.
 
 
 
While I would recommend using the "if rising_edge(clock)" syntax for synchronous processes, as you also find it in the ISE language templates, you can also use "wait until rising_edge(clock) for synthesis. (But that was not your question.)
 
But even if you use these valid constructs in a wrong way the compiler will give you an error message.
Sometimes because you composed a code that is no valid synchronous description according to the VHDL synthesis standard, sometimes because the hardware can not implement it (e.g. dual edge FFs).
 
Have a nice synthesis
  Eilert
 

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