Xilinx Block RAM能否在一个时钟周期内始终如一地返回数据？

我在Xilinx Spartan-3E（XC3S500E）上使用Verilog创建了一个使用多个双端口Block RAM的设计，所有这些都通过Verilog原语实例化，例如RAMB16_S18_S18。
我使用一个端口进行读取和写入（使用写入启用），第二个端口仅用于读取（通过将WEB设置为0）。
两个端口共享相同的时钟。
Block RAM设置为18位宽，但我忽略了奇偶校验数据（即，不使用其输出值，并始终将零写入奇偶校验位）
我正在使用Xilinx ISE 13.4并使用默认设置的GUI工作流程进行合成/实现。
（非默认设置，例如积极的时序优化和/或物理综合在这个问题上没有区别）
我对我的唯一时钟网有时序限制，并且它与实际时钟信号一致（约束是50MHz，我正在使用的开发板上有50MHz时钟，并且时序报告指出
我的设计的最大频率是64.7MHz。时钟通过一个时钟多路复用器用作时钟使能，然后转到我的整个逻辑。
在我的代码中，我有一个状态机，它有三种状态（在Block RAM使用的相同50MHz时钟的上升沿转换）：
将地址写入连接到端口A和B的地址输入的寄存器。
读取数据，对其执行一些逻辑操作，并将其写入与块RAM上的DIA（A中的数据）相连的reg [15：0]（地址不变）。
打开端口A的写入启用。
将一些IO引脚读入不相关的寄存器。
关闭块RAM写使能。
这在ISim中的行为仿真中始终如一，并且（尽管它比模拟器的测试少）在端口A上始终成功。端口B具有相同的逻辑（简单地用于地址的位切片，以及用于SSR，SRVAL，INIT的相同配置）
）但在这一个时钟周期内没有成功读取。
通过简单地在1和2之间添加额外状态（因此为地址提供超过一个整个时钟周期的建立时间），设计可以工作，尽管作为FPGA开发的学习者，我想知道为什么以及如何避免它。
根据Xilinx数据表DS312和其中的时序图，这应该是使用Block RAM的可接受方式。
在同一数据表中给出了设置和保持时间，但ISE工具应该已经知道它们并在时序分析期间应用它们，如果我没有弄错的话。
另外，我已经重新阅读了UG331（Spartan-3 Generation用户指南）的Block RAM部分几次，并且在指令和块RAM的使用之间找不到任何不一致。
最慢路径的时间报告列表神秘地没有列出任何进入违规RAM端口的路径。
如果有人可以提出建议，那将是值得赞赏的，因为我花了很长时间调试这个并担心我可能会犯一些初学者的错误。
如果需要任何其他信息，请告诉我，以便我可以提供。



以下为原文

I'm creating a design using Verilog on a Xilinx Spartan-3E (XC3S500E) that uses multiple dual-port block RAMs, all instantiated through Verilog primitives such as RAMB16_S18_S18. I am using one port for both reading and writing (using write-enable) and the second for only reading (by setting WEB to 0). Both ports share the same clock. The block RAM is set to 18-bit wide, but I am ignoring the parity data (that is, not using its output value, and always writing zeros to parity bits)
I am using Xilinx ISE 13.4 and synthesizing/implementing using the GUI workflow with default settings. (non-default settings such as aggressive timing optimization and/or physical synthesis did not have a difference in regard to this issue)
I have timing constraints made for my one and only clock net, and it is consistent with the actual clock signal being put in (the constraint is for 50MHz, there is a 50MHz clock on the dev board I am using, and the timing report states that the maximum frequency for my design is 64.7MHz. The clock runs through a clock mutliplexer used as a clock enable, before going to the entirety of my logic.
In my code, I have a state machine that has three states (transitioning on rising edge of the same 50MHz clock that the block RAM uses):

• Write address to a register connected to the address inputs of ports A and B.
• Read data, perform some logic operations on it, and write it to a reg[15:0] that is connected to DIA (data in A) on the block RAM (with the address not changing). Turn on write enable for port A.
• Read some IO pins into unrelated registers. Turn off block RAM write enable.
  

This consistently succeeds in a behavioral simulation in ISim, and (although it had less testing than the simulator) consistently succeeds on port A. Port B has identical logic (simply bit-slicing for address, and the same configuration for SSR, SRVAL, INIT) but does not succeed in reading during this one clock cycle. By simply adding an extra state between 1 and 2 (thus giving a setup time of over one entire clock cycle for the address) the design works, although as a learner of FPGA development I would like to know why and how to avert it.
According to Xilinx datasheet DS312 and timing diagrams within, this should be an acceptable way of using the block RAM. There are setup and hold times given in that same datasheet, but the ISE tools should already be aware of them and apply them during timing analysis, if I'm not mistaken. Additionally, I've re-read the block RAM section of UG331 (Spartan-3 Generation User Guide) a few times and could not find any inconsistencies between the instructions and my use of the block RAM.
The timing report list of the slowest paths mysteriously does not list any paths going to the offending RAM port.
If someone could make a recommendation, that would be appreciated, as I've spent quite a while debugging this and fear that I might be making some beginners' mistake. If any additional info is needed, please let me know so I can provide it.