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我有一个带有8个GTX TX通道的Virtex-6 VC6VLX240TFF1156-3项目。
我正在使用EDK 13.3。 根据coregen示例HDL,每个GTX TX通道都有一个相关的用户时钟(通过BUFG),我的代码和GTXE1都使用它。 导出的用户时钟中的一个(且仅一个)以下列方式失败放置: 警告:地点:1146 - 无法安排的位置! 已发现GT / BUFGCTRL时钟组件对未放置在可路由的GT / BUFGCTRL站点对上。 GT组件放置在现场。 相应的BUFGCTRL组件放置在现场。 如果GT和BUFGCTRL都放置在设备的同一半(TOP或BOTTOM)中,则该对可以使用GT和时钟缓冲器之间的快速路径。 您可能想要分析存在此问题的原因并进行更正。 这通常是一个错误,但CLOCK_DEDICATED_ROUTE约束已应用于COMP.PIN,允许您的设计继续。 此约束禁用与指定的COMP.PIN相关的所有时钟布局器规则。 PAR中的此放置是不可用的,因此,应在您的设计中修复此错误情况。 请注意,在我将CLOCK_DEDICATED_ROUTE限定符添加到我的UCF之前,这是致命错误。 三个问题: 这是AR#43894的副本吗? 该公告表明这个问题不应该存在于13.3中,所以我很困惑。 如果我在我的UCF中使用CLOCK_DEDICATED_ROUTE修改解决这个问题,这个特定的GTXE1是否可靠? 如果没有,那我该怎么办? 谢谢, 斯泰西 以上来自于谷歌翻译 以下为原文 I have a Virtex-6 VC6VLX240TFF1156-3 project with 8 GTX TX channels. I'm using EDK 13.3. Per the coregen example HDL, each GTX TX channel has an associated user clock (via a BUFG) which is utilized by both my code and the GTXE1. One (and only one) of the derived user clocks is failing placement in the following way: WARNING:Place:1146 - Unroutable Placement! A GT / BUFGCTRL clock component pair have been found that are not placed at a routable GT / BUFGCTRL site pair. The GT component Note, that this was a fatal error until I added the CLOCK_DEDICATED_ROUTE qualifier to my UCF. Three questions:
Stacey |
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7个回答
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GT被放置在设备的上半部分,而BUFG被放置在设备的下半部分。
这会产生无法使用专用时钟资源的情况,因此设置CLOCK_DEDICATED_ROUTE = FALSE将允许此放置,并允许工具使用常规资源路由将时钟从GTX路由到BUFG。 这将导致不可预测的路由延迟,如错误消息中所述,因为每次重新运行路由器时路由可能会更改。 由于不使用专用资源,它还可能会给您的时钟带来更多失真和/或抖动。 该约束旨在允许您放置和布线您的设计,然后在FPGA编辑器中检查设计,以查看导致无法布置的位置的原因。 在这种情况下,您的GTX位于站点GTXE1_X0Y12(上半部分),BUFG位于BUFG_X0Y11(下半部分)。 限制BUFG到任何上半部分站点的位置应允许此设计路由(“BUFGCTRL_X0Y16”到BUFGCTRL_X0Y31) 现在,如果您使用的是BUFGMUX,那么您还必须确保BUFG的两个源也位于设备的上半部分。 当你使用BUFGMUX在设备的下半部分有一个输入而另一个输入来自设备的上半部分时,这些工具会产生这种无法处理的情况。如果你使用的是固定的引脚排列并且无法改变它,那么你将需要 通过使用本地互连来决定哪个时钟受影响最小。 在原帖中查看解决方案 以上来自于谷歌翻译 以下为原文 The GT is placed in the top half of the device while the BUFG is being placed in the bottom half of the device. This creates a situation where the dedicated clock resources cannot be used so setting CLOCK_DEDICATED_ROUTE=FALSE will allow this placement and will let the tools route the clock from the GTX to the BUFG using general resource routing. This will lead to unpredictable routing delays, as generally stated in the error message, since the route will likely change each time you rerun the router. It will also potentially introduce more distortion and or jitter to your clock since dedicated resources are not used. The constraint was designed to allow you to place and route your design then examine the design in FPGA Editor to see what caused the unroutable placement. In this case your GTX is placed at site GTXE1_X0Y12 (Top Half) and the BUFG is placed at BUFG_X0Y11 (Bottom Half). Location constraining the BUFG to any of the top half sites should allow this design to route ( "BUFGCTRL_X0Y16" through BUFGCTRL_X0Y31) Now if you are using a BUFGMUX then you also have to make sure both sources of the BUFG are also in the top half of the device. The tools will create this unroutable situation when you use a BUFGMUX with one input in the bottom half of the device and the other input sourced from the top half of the device. If you are using a fixed pinout and cannot change it then you will need to decide which of the clocks will be least affected by using local interconnect. View solution in original post |
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GT被放置在设备的上半部分,而BUFG被放置在设备的下半部分。
这会产生无法使用专用时钟资源的情况,因此设置CLOCK_DEDICATED_ROUTE = FALSE将允许此放置,并允许工具使用常规资源路由将时钟从GTX路由到BUFG。 这将导致不可预测的路由延迟,如错误消息中所述,因为每次重新运行路由器时路由可能会更改。 由于不使用专用资源,它还可能会给您的时钟带来更多失真和/或抖动。 该约束旨在允许您放置和布线您的设计,然后在FPGA编辑器中检查设计,以查看导致无法布置的位置的原因。 在这种情况下,您的GTX位于站点GTXE1_X0Y12(上半部分),BUFG位于BUFG_X0Y11(下半部分)。 限制BUFG到任何上半部分站点的位置应允许此设计路由(“BUFGCTRL_X0Y16”到BUFGCTRL_X0Y31) 现在,如果您使用的是BUFGMUX,那么您还必须确保BUFG的两个源也位于设备的上半部分。 当你使用BUFGMUX在设备的下半部分有一个输入而另一个输入来自设备的上半部分时,这些工具会产生这种无法处理的情况。如果你使用的是固定的引脚排列并且无法改变它,那么你将需要 通过使用本地互连来决定哪个时钟受影响最小。 以上来自于谷歌翻译 以下为原文 The GT is placed in the top half of the device while the BUFG is being placed in the bottom half of the device. This creates a situation where the dedicated clock resources cannot be used so setting CLOCK_DEDICATED_ROUTE=FALSE will allow this placement and will let the tools route the clock from the GTX to the BUFG using general resource routing. This will lead to unpredictable routing delays, as generally stated in the error message, since the route will likely change each time you rerun the router. It will also potentially introduce more distortion and or jitter to your clock since dedicated resources are not used. The constraint was designed to allow you to place and route your design then examine the design in FPGA Editor to see what caused the unroutable placement. In this case your GTX is placed at site GTXE1_X0Y12 (Top Half) and the BUFG is placed at BUFG_X0Y11 (Bottom Half). Location constraining the BUFG to any of the top half sites should allow this design to route ( "BUFGCTRL_X0Y16" through BUFGCTRL_X0Y31) Now if you are using a BUFGMUX then you also have to make sure both sources of the BUFG are also in the top half of the device. The tools will create this unroutable situation when you use a BUFGMUX with one input in the bottom half of the device and the other input sourced from the top half of the device. If you are using a fixed pinout and cannot change it then you will need to decide which of the clocks will be least affected by using local interconnect. |
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除了Lyman的评论之外,我还要补充说,除非您使用13.3之前版本中提到的核心,否则答复记录不适用于您。
这是一个糟糕的核心生成(连接或约束)而不是工具问题的情况。 如果你没有使用那个核心,那么你的根本原因是不同的,但可能是相似的。 您需要确定导致布局器无法满足GT / BUFGCTRL对的放置要求的连接或约束。 为此,使用提供的约束覆盖时钟专用路径错误,然后在FPGA编辑器中检查生成的不可路由设计,以检查两个组件的连接性。 以上来自于谷歌翻译 以下为原文 In addition to Lyman's comments I'll just add that the Answer Record doesn't apply to you unless you are using the core mentioned in a version prior to 13.3. That was a case of bad core generation (either connectivity or constraints) and not a tool issue. If you are not using that core then your root cause is different but may be similar. You need to determine what connectivity or constraint is causing the placer to be unable to satisfy the placement requirements of the GT/BUFGCTRL pair. To do that, override the clock dedicated route error with the constraint provided and then examine the resulting unroutable design in FPGA Editor to examine the connectivity of the two components. |
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我只是将coregen的示例Verilog输出集成到我的8通道GTX项目中。
GTXE1原语依赖于正确定位的BUFG来提供用户时钟,然后我可以使用该时钟提供并行数据以供原语序列化。 正如我现在所希望的那样,其含义是GTXE1实际上位于芯片上,使得coregen示例代码中的BUFG也必须具有位置限制,对吗? 如果是这样,我本以期望映射器正确处理这种情况。 或者,或者我希望示例UCF文件将8个BUFG约束到有效位置。 (这个特殊问题,与其他正在进行的问题同时发生,现在已经将我的日程安排了几天。) 斯泰西 以上来自于谷歌翻译 以下为原文 I'm simply integrating coregen's example Verilog output into my 8 channel GTX project. The GTXE1 primitive relies on a correctly located BUFG to provide a user clock with which I can then provide parallel data for serialization by the primitive. The implication, as I now hopefully understand, is that GTXE1's are physically located on the die in such a way that the BUFG in the coregen sample code must also have location constraints, right? If so, I would have expected the mapper to correctly deal with this situation. Either that, or I would expect the example UCF file to constrain the 8 BUFGs to valid locations. (This particular problem, simultaneous with this other ongoing problem, have now set my schedule back several days.) Stacey |
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如果您能够添加约束以获得合法放置,那么这将被视为Placer错误的证据。
它应该能够自动找到该解决方案。 以上来自于谷歌翻译 以下为原文 If you are able to add a constraint to get a legal placement, then that would be considered evidence of a Placer bug. It should have been able to find that solution automatically. |
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嗨,
我遇到了同样的问题。 我正在使用kc705和xps14.6。 我找不到在xps中启动fpga编辑器的方法,你能告诉我如何启动它吗? 谢谢。 贾森 以上来自于谷歌翻译 以下为原文 Hi, I'm meeting the same problem. I'm using kc705 and xps14.6. I can't find the way to launch fpga editor in xps, can you show me how to launch it? Thanks. Jason |
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