[问答]

在AXI QUAD SPI的综合放置中遇到错误

问答对人有帮助，内容完整，我也想知道答案 0 我在AXI QUAD SPI的综合/放置中遇到以下错误我为ext_spi_clk创建了外部端口，为SPI_O创建了接口端口。 [放置30-574] IO引脚和BUFG之间的布线布局不佳。如果此子设计可接受此子优化条件，则可以使用.xdc文件中的CLOCK_DEDICATED_ROUTE约束将此消息降级为WARNING。但是，强烈建议不要使用此覆盖。这些示例可以直接在.xdc文件中使用，以覆盖此时钟规则。 ext_spi_clk_IBUF_inst（IBUF.O）被锁定到IOB_X1Y46并且ext_spi_clk_IBUF_BUFG_inst（BUFG.I）由clockplacer临时放置在BUFGCTRL_X0Y0上 [放置30-99] Placer因错误而失败：'IO Clock Placer failed'请在放置期间查看所有ERROR，CRItiCAL WARNING和WARNING消息，以了解失败原因。 [Common 17-69]命令失败：Placer无法放置所有实例 --------------------------------- [Common 17-55]'set_property'需要至少一个对象。 [“/home/cpatel/DataEngine/cpu_linux_2/cpu_linux_2.srcs/constrs_1/imports/cpu_linux/cpu_linux.xdc":45]set_property LOC AF15 [get_ports {spi_0_io0_io}]; [Common 17-55]'set_property'需要至少一个对象。 [“/home/cpatel/DataEngine/cpu_linux_2/cpu_linux_2.srcs/constrs_1/imports/cpu_linux/cpu_linux.xdc":46]set_property IOSTANDARD LVCMOS15 [get_ports spi_0_io0_io]; ----------------- [Common 17-55]'get_property'需要至少一个对象。 [“/home/cpatel/DataEngine/cpu_linux_2/cpu_linux_2.srcs/sources_1/bd/cpu_uart/ip/cpu_uart_axi_quad_spi_0_0/cpu_uart_axi_quad_spi_0_0_clocks.xdc":52] set_max_delay -from [get_cells -hierarchical -filter {NAME =〜* RX_FIFO_II / USE_2N_DEPTH。 V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM / inst_fifo_gen / gconvfifo.rf / grf.rf / gntv_or_sync_fifo.gcx.clkx / wr_pntr_gc_reg }] -to [get_cells -hierarchical -filter {NAME =〜* RX_FIFO_II / USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM / inst_fifo_gen / gconvfifo .rf / grf.rf / gntv_or_sync_fifo.gcx.clkx / gsync_stage 。rd_stg_inst / Q_reg_reg }] -datapath_only [get_property -min PERIOD $ clk_domain_ext_spi_clk] [Common 17-55]'get_property'需要至少一个对象。 [“/home/cpatel/DataEngine/cpu_linux_2/cpu_linux_2.srcs/sources_1/bd/cpu_uart/ip/cpu_uart_axi_quad_spi_0_0/cpu_uart_axi_quad_spi_0_0_clocks.xdc":55] set_max_delay -from [get_cells -hierarchical -filter {NAME =〜* TX_FIFO_II / USE_2N_DEPTH。 V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM / inst_fifo_gen / gconvfifo.rf / grf.rf / gntv_or_sync_fifo.gcx.clkx / rd_pntr_gc_reg }] -to [get_cells -hierarchical -filter {NAME =〜* TX_FIFO_II / USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM / inst_fifo_gen / gconvfifo .rf / grf.rf / gntv_or_sync_fifo.gcx.clkx / gsync_stage .wr_stg_inst / Q_reg_reg }] -datapath_only [get_property -min PERIOD $ clk_domain_ext_spi_clk] 以上来自于谷歌翻译以下为原文 I am gettng the following errors in synthesis/place for AXI QUAD SPI I have created external port for the ext_spi_clk and interface port for SPI_O. [Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule. < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets ext_spi_clk_IBUF] > ext_spi_clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y46 and ext_spi_clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 [Place 30-99] Placer failed with error: 'IO Clock Placer failed' Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure. [Common 17-69] Command failed: Placer could not place all instances ---------------------------------[Common 17-55] 'set_property' expects at least one object. ["/home/cpatel/DataEngine/cpu_linux_2/cpu_linux_2.srcs/constrs_1/imports/cpu_linux/cpu_linux.xdc":45] set_property LOC AF15 [get_ports {spi_0_io0_io}] ; [Common 17-55] 'set_property' expects at least one object. ["/home/cpatel/DataEngine/cpu_linux_2/cpu_linux_2.srcs/constrs_1/imports/cpu_linux/cpu_linux.xdc":46] set_property IOSTANDARD LVCMOS15 [get_ports spi_0_io0_io] ; ----------------- [Common 17-55] 'get_property' expects at least one object. ["/home/cpatel/DataEngine/cpu_linux_2/cpu_linux_2.srcs/sources_1/bd/cpu_uart/ip/cpu_uart_axi_quad_spi_0_0/cpu_uart_axi_quad_spi_0_0_clocks.xdc":52] set_max_delay -from [get_cells -hierarchical -filter {NAME =~RX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_reg}] -to [get_cells -hierarchical -filter {NAME =~RX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage.rd_stg_inst/Q_reg_reg}] -datapath_only [get_property -min PERIOD $clk_domain_ext_spi_clk] [Common 17-55] 'get_property' expects at least one object. ["/home/cpatel/DataEngine/cpu_linux_2/cpu_linux_2.srcs/sources_1/bd/cpu_uart/ip/cpu_uart_axi_quad_spi_0_0/cpu_uart_axi_quad_spi_0_0_clocks.xdc":55] set_max_delay -from [get_cells -hierarchical -filter {NAME =~TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_reg}] -to [get_cells -hierarchical -filter {NAME =~TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage.wr_stg_inst/Q_reg_reg}] -datapath_only [get_property -min PERIOD $clk_domain_ext_spi_clk] 0
2018-10-18 14:37:32　　评论淘帖0 邀请回答您可以邀请以下用户，快速回答问题 × asd008 该类别下有 32 个回答。邀请回答 aaaa321 该类别下有 27 个回答。邀请回答 doublelove 该类别下有 26 个回答。邀请回答 vynywrwr 该类别下有 21 个回答。邀请回答 hgjhgd 该类别下有 19 个回答。邀请回答 bwerwer 该类别下有 18 个回答。邀请回答 hanyan533 该类别下有 18 个回答。邀请回答 Jaionm 该类别下有 18 个回答。邀请回答 handsomelchcpp 该类别下有 17 个回答。邀请回答 wang2222222 该类别下有 17 个回答。邀请回答 binro 该类别下有 16 个回答。邀请回答 ningee 该类别下有 16 个回答。邀请回答 myf888 该类别下有 15 个回答。邀请回答 wznnzw 该类别下有 15 个回答。邀请回答 zcy615 该类别下有 14 个回答。邀请回答 wanglinhua2627 该类别下有 14 个回答。邀请回答 guotong1984 该类别下有 14 个回答。邀请回答 yhxc 该类别下有 14 个回答。邀请回答 armortech 该类别下有 14 个回答。邀请回答 60user25 该类别下有 14 个回答。邀请回答举报石建军相关推荐 • Axi quad spi怎么作为从属设备？ 3357 • [放置30-73] axi_quad_spi版本3.2的寄存器'IO1_I_REG'的约束无效 1719 • [放置30-73]SPI接口IP，如何解决这个严重警告？ 6926 • Vivado无法放置任何时钟资源 10389 • 怎么使用AXI Quad SPI IP Core对带有PROM文件的SPI Flash进行编程 4532 • Spi模式設定(PYNQ-Z2) 11816 • 求Vivado 2016.1中开发了AXI外设调试遇到错误的解决办法？ 6860 • 哪位大神可以分享Quad-SPI命令序列？ 998 • Vivado 16.2放置错误（30-512） 6091 • 如何在未使用的QUAD和部分使用的QUAD中连接RX，TX，MGTREFCLK？ 2837 2个回答

答案对人有帮助，有参考价值 0 转向实施以上来自于谷歌翻译以下为原文 Moving to Implementation

2018-10-18 14:52:10 评论举报李裕伦

答案对人有帮助，有参考价值 0 您需要告诉我们更多关于您要做什么的信息。您是否尝试实现SPI主设备或SPI从设备？从这里的一些消息来看，您似乎正在尝试将SPI时钟作为输入，这将为SPI从设备完成。如果是这样，那么你有两个选择： - 将其带入具有时钟功能的引脚，将其路由到BUFG（可能包括MMCM或PLL）并使用时钟为IOB FF提供时钟 - 时钟必须位于时钟引脚上 - 使用更高速度的内部时钟对时钟和数据进行过采样对于过采样：SPI接口往往很慢（我们需要知道速度有多快）。如果它们小于10MHz（可能是20MHz）范围，并且您可以访问更快的时钟（比如100MHz），那么您所做的是将时钟和数据作为常规信号，亚稳态解决它们，然后寻找同步“时钟”的边沿确定何时采样输入数据并输出输出数据。如果这是SPI主设备，那么时钟应该是输出。外部设备需要一个“时钟” - 一个周期性的信号，与其他接口引脚同步。但是，通常，这个转发到SPI引脚的“时钟”实际上并不用作FPGA内部的时钟。通常，内部（可能更高速）时钟用于生成转发时钟和数据。如果是这样，那么FPGA中生成的供SPI设备使用的“时钟”应该只是一个输出端口 - 您不应该尝试使用这个“时钟”为FPGA内部的任何逻辑提供时钟。 Avrum 以上来自于谷歌翻译以下为原文 You need to tell us more about what you are trying to do. Are you trying to implement a SPI master or a SPI slave? From some of the messages here, it looks like you are trying to bring the SPI clock in as an input, which would be done for a SPI slave. If so, then you have two options: - bring it in on a clock capable pin, route it to a BUFG (possibly including an MMCM or PLL) and clock an IOB FF with the clock - the clock must be on a clock capable pin - oversample both the clock and data with a higher speed internal clock For oversampling: SPI interfaces tend to be slow (we need to know how fast). If they are less than th 10MHz (maybe 20MHz) range, and you have access to a faster clock (say 100MHz), then what you do is bring both the clock and data in as regular signals, metastability resolve them, then look for the edges of the synchronized "clock" to determine when to sample input data and put out output data. If this is a SPI master, then the clock should be an output. The external device requires a "clock" - a signal that is periodic and synchronous to its other interface pins. However, generally, this forwarded "clock" to the SPI pin is not actually used as a clock inside the FPGA. Often, an internal (possibly higher speed) clock is used to generate both the forwarded clock and data. If so, then the "clock" generated in the FPGA for use by the SPI device should be an output port only - you should not be trying to clock any logic inside the FPGA using this "clock". Avrum

2018-10-18 15:09:30 评论举报陈玉筠