微晶时钟输入不路由

感谢您的帮助;
你肯定让我走上了正确的道路。
我尝试使用从输入引脚到微灯时钟输入的IBUFG，但仍然说它无法路由。
然而，我能够通过首先将输入引脚发送到IBUF，然后从那里发送到BUFG，最后发送到微型发光器来使其工作。
再次感谢。
在原帖中查看解决方案



以下为原文

Thank you for your help; you definitely set me on the right path.
 
I tried using an IBUFG from the input pin to the microblaze clock input, but that still said it was unable to route.
 
However, I was able to get it to work by first sending the input pin to an IBUF, and then from there to a BUFG, and finally to the microblaze.
 
Thanks again.
View solution in original post

我猜想F5不是您正在使用的零件和包的时钟输入的有效位置。
但是由于你还没有发布这些细节，所以无法确定。
------------------------------------------“如果它不起作用
模拟，它不会在板上工作。“



以下为原文

I would guess that F5 is not a valid location for a clock input for the part and package that you are using. But as you have not posted those details, it is impossible to be sure.

------------------------------------------
"If it don't work in simulation, it won't work on the board."

谢谢，但遗憾的是F5是一个用户IO引脚，只需使用Verilog即可作为时钟输入工作。
但是通过将其作为Microblaze的时钟输入，它表示它无法路由它。我是新手，所以如果有更多信息我应该提供以帮助隔离问题，请告诉我。



以下为原文

Thank you, but unfortunately F5 is a user IO pin that works fine as a clock input when just using Verilog.  But by making it the clock input for a Microblaze, it says that it is not able to route it.

I am new to this, so please let me know if there is more information I should provide to help isolate the problem.

kdc71726写道：谢谢，但不幸的是F5是一个用户IO引脚，只使用Verilog作为时钟输入工作正常。
但是通过将其作为Microblaze的时钟输入，它表示它无法路由它。我是新手，所以如果有更多信息我应该提供以帮助隔离问题，请告诉我。
什么是确切的错误消息？
----------------------------是的，我这样做是为了谋生。



以下为原文

kdc71726 wrote:
Thank you, but unfortunately F5 is a user IO pin that works fine as a clock input when just using Verilog. But by making it the clock input for a Microblaze, it says that it is not able to route it.

I am new to this, so please let me know if there is more information I should provide to help isolate the problem.

What's the exact error message?
----------------------------Yes, I do this for a living.

XPS给出的错误是：
错误：Xflow  - 程序par返回错误代码30.中止流程执行...
make：*** [__xps / microblaze1_routed]错误1
和警告：
警告：路由：436  - 路由器检测到一个或多个连接的不可路由情况。
路由器将完成 
设计的其余部分并将它们保留为未布线状态。
此行为的原因是放置问题 
或不可路由的放置约束。
为了让您使用FPGA编辑器来隔离问题，以下是一个列表 
（最多10个）这种不可连接的连接：
警告：参数：100  - 设计未完全路由。
有1个信号没有 
在这个设计中完全路由。
请参阅“microblaze1.unroutes”文件以获取列表 
所有未经发布的信号。
检查PAR报告中可能包含的其他警告 
说明为什么这些网是无法清除的。
这些网也可以评估 
在FPGA编辑器中，通过在列表窗口中选择“未布线的网络”。
希望这可以帮助。



以下为原文

The error XPS gives is:
 
ERROR:Xflow - Program par returned error code 30. Aborting flow execution... make: *** [__xps/microblaze1_routed] Error 1 and the warnings:
 
WARNING:Route:436 - The router has detected an unroutable situation for one or more connections. The router will finish   the rest of the design and leave them as unrouted. The cause of this behavior is either an issue with the placement   or unroutable placement constraints. To allow you to use FPGA editor to isolate the problems, the following is a list   of (up to 10) such unroutable connections:WARNING:Par:100 - Design is not completely routed. There are 1 signals that are not   completely routed in this design. See the "microblaze1.unroutes" file for a list of   all unrouted signals. Check for other warnings in your PAR report that might   indicate why these nets are unroutable. These nets can also be evaluated   in FPGA Editor by selecting "Unrouted Nets" in the List Window. 
Hope this helps.

我会猜测IBUF输出需要一个BUFG来驱动时钟分配网络，而XST决定不自己推断BUFG缓冲区。
或者将IBUF更改为IBUFG。
只是一个猜测......
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

I'll make a wild guess that the IBUF output needs a BUFG to drive the clock distribution network, and XST has decided not to infer the BUFG buffer on its own.
 
Or change the IBUF to an IBUFG.
 
Just a guess...
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

谢谢。
我很遗憾地问，但你如何在XPS中进行这些更改？



以下为原文

Thank you.  And I'm sorry to ask, but how would you make these changes in XPS?

谢谢。
我很遗憾地问，但你如何在XPS中进行这些更改？
我从未使用过MicroBlaze，所以我不熟悉核心设计文件和相关的文件结构。
我猜你的最新帖子，你也不熟悉MicroBlaze设计文件。
所以我不能给你一步一步的建议。
一般来说，您的时钟输入引脚连接到IBUF原语的输入。
我建议（猜测）的补救办法是，这个IBUF原语应该用IBUFG原语替换。
我不知道您的源代码文件是Verilog还是VHDL。
您可以在ISE语言模板（ISE应用程序顶部的灯泡图标）中找到IBUF和IBUFG原语的示例。
在Verilog中，这是一个IBUF原语实例化模板。 
IBUF IBUF_inst（ 
.O（output_signame），//缓冲区输出 
.I（input_signame）//缓冲区输入（直接连接到顶级端口） 
）;
在Verilog中，这是一个IBUFG原语实例化模板。 
IBUFG IBUFG_inst（ 
.O（output_signame），//时钟缓冲输出 
.I（input_signame）//时钟缓冲输入（直接连接到顶级端口） 
）;
我希望您的问题的解决方案就像在源代码中定位时钟输入缓冲区（IBUF）并编辑代码来实例化IBUFG而不是IBUF一样简单。
在这种情况下，您只需将文本“IBUF”替换为“IBUFG”即可。
很抱歉，我无法向您提供更好或更具体的建议。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

Thank you. And I'm sorry to ask, but how would you make these changes in XPS?
 
I've never used MicroBlaze, so I am unfamiliar with the core design files and associated file structure.  I'm guessing from your latest post that you are also unfamiliar with the MicroBlaze design files.  So I cannot give you step by step advice.
 
Generally speaking, your clock input pin is connected to the input of an IBUF primitive.  My suggested (guess) remedy is that this IBUF primitive should be replaced with an IBUFG primitive.  I do not know whether your source code files are Verilog or VHDL.  You can find examples of the IBUF and IBUFG primitives in the ISE language templates (the light bulb icon at the top of the ISE application).
 
In Verilog, this is an IBUF primitive instantiation template.
   IBUF IBUF_inst (      .O  (output_signame),     // Buffer output      .I  (input_signame)        // Buffer input (connect directly to top-level port)   ); 
In Verilog, this is an IBUFG primitive instantiation template.
   IBUFG  IBUFG_inst (      .O  (output_signame), // Clock buffer output      .I  (input_signame)  // Clock buffer input (connect directly to top-level port)   ); 
I'm hoping that the solution to your problem is as simple as locating the clock input buffer (IBUF) in your source code and editing the the code to instantiate an IBUFG instead of an IBUF. In this case, you would simply replace the text "IBUF" with "IBUFG". I'm sorry that I cannot provide you with better or more specific advice.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

感谢您的帮助;
你肯定让我走上了正确的道路。
我尝试使用从输入引脚到微灯时钟输入的IBUFG，但仍然说它无法路由。
然而，我能够通过首先将输入引脚发送到IBUF，然后从那里发送到BUFG，最后发送到微型发光器来使其工作。
再次感谢。



以下为原文

Thank you for your help; you definitely set me on the right path.
 
I tried using an IBUFG from the input pin to the microblaze clock input, but that still said it was unable to route.
 
However, I was able to get it to work by first sending the input pin to an IBUF, and then from there to a BUFG, and finally to the microblaze.
 
Thanks again.

IBUFG只是一个用于“建议”工具将PAD放在时钟引脚上的组件。
这主要用于Xilinx引入BUFR的Virtex-4之前的架构。
如果将BUFR置于具有时钟功能并且应该使用但不需要它，则BUFR确实可以更好地工作。
因此，IBUFG不会强制将时钟置于具有时钟功能的PAD上，尽管工具总是尽可能使用时钟垫。
如果你想推断IBUF + BUFG那么你可以使用BUFGP。
这也是Virtex2中使用的旧缓冲区类型，但仍然有效。
如果你想在你的BUFG上使用位置约束，它可能会导致问题，因为BUFG基本上是低音的，然后组件名称可以在一次合成运行中改变到下一次。
启动BUFG是一个很好的解决方案，可以插入BUFG，它将始终具有可重复的实例名称，以防您需要放置它。



以下为原文

An IBUFG is just a component that is used to "suggest" that the tools place the PAD on a clock capable pin. This was primarily used for architecturees prior to Virtex-4 where Xilinx introduced the BUFR.  The BUFR does work better if it is placed on a Clock Capable and should be used but it is not required.  Due to this the IBUFG does not force the clock to be placed on an clock capable PAD, though tools will always try to use the clock pad when possible.
 
If you want to infer an IBUF + BUFG then you can use a BUFGP.  This also an old buffer type, used in Virtex2, but will still work.  It can lead to problems if you want to use Location Constraints on your BUFG since the BUFG is essentially inferrred and then component name can change for one synthesis run to the next.
 
Intiating the BUFG is a good solution to get the BUFG inserted and it will always have a repeatable instance name in case you need to place it.