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我正在修改已经放置在电路板上的FPGA的设计。 该项目必须从旧版本(9.1,我相信)升级为ISE 10.1。 升级后,我能够成功合成并实施项目。 到目前为止,我已经进行了一些设计更改并完成了几个实现错误,但我目前仍然遇到以下PAR错误: 错误:放置:704 - IPAD组件“FPGA_CLK_N”被锁定到MONITORIPAD站点“IOB_X1Y98”。 IPAD类型的组件无法锁定到MONITORIPAD类型的站点 错误:放置:704 - IPAD组件“FPGA_CLK_P”被锁定到MONITORIPAD站点“IOB_X1Y99”。 IPAD类型的组件无法锁定到MONITORIPAD类型的站点 任何人都可以提出一些如何解决这个问题的建议吗? 我的ucf文件中的相关信息是: Net“FPGA_CLK_P”TNM_NET = FPGA_CLK_P; tiMESPEC TS_FPGA_CLK_P = PERIOD FPGA_CLK_P 6.4 ns高50%; 净“FPGA_CLK_N”TNM_NET = FPGA_CLK_N; TIMESPEC TS_FPGA_CLK_N = PERIOD FPGA_CLK_N 6.4 ns高50%; NET“FPGA_CLK_P”LOC = A14 | IOSTANDARD =“LVDS_25”| DIFF_TERM = TRUE; NET“FPGA_CLK_N”LOC = A13 | IOSTANDARD =“LVDS_25”| DIFF_TERM = TRUE; 正如我所说,这是一块已经在板上的芯片,因此更改引脚排列不是一种选择。 在此先感谢任何帮助...... 以上来自于谷歌翻译 以下为原文 Hello- I am modifyng a design for an FPGA that was already placed on a board. The project had to be upgraded for ISE 10.1 from an older version (9.1, I believe). I was able to successfully synthesize and implement the project after it was upgraded. I had made some design changes and have worked through a couple of implementation errors so far, but I'm currently stuck on the following PAR error: ERROR:Place:704 - IPAD component "FPGA_CLK_N" is locked to MONITORIPAD site "IOB_X1Y98". A component of type IPAD can not be locked to a site of type MONITORIPAD ERROR:Place:704 - IPAD component "FPGA_CLK_P" is locked to MONITORIPAD site "IOB_X1Y99". A component of type IPAD can not be locked to a site of type MONITORIPAD Can anyone offer some suggestions as to how to resolve this? The relevant info from my ucf file is: Net "FPGA_CLK_P" TNM_NET = FPGA_CLK_P; TIMESPEC TS_FPGA_CLK_P = PERIOD FPGA_CLK_P 6.4 ns High 50%; Net "FPGA_CLK_N" TNM_NET = FPGA_CLK_N; TIMESPEC TS_FPGA_CLK_N = PERIOD FPGA_CLK_N 6.4 ns High 50%; NET "FPGA_CLK_P" LOC = A14 | IOSTANDARD = "LVDS_25" | DIFF_TERM = TRUE; NET "FPGA_CLK_N" LOC = A13 | IOSTANDARD = "LVDS_25" | DIFF_TERM = TRUE; As I said, this is a chip that is already on a board, so changing the pinout is not an option. Thanks in advance for any assistance... |
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尝试清理整个项目,然后重建。
-一个 ----------------------------是的,我这样做是为了谋生。 以上来自于谷歌翻译 以下为原文 Try cleaning the entire project, and rebuilding. -a ----------------------------Yes, I do this for a living. |
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感谢您的快速回复。
对不起我的回复延迟......我刚回到办公室。 我确实尝试过清理和重建项目,但这对PAR错误没有影响。 在我遇到这个当前问题之前,清理/重建确实帮我解决了一两个错误。 再次感谢...还有其他想法吗? 以上来自于谷歌翻译 以下为原文 Thanks for the quick reply. Sorry for the delay of my response...I'm just getting back into the office. I did try cleaning and rebuilding the project already, but that had no effect on the PAR error. Cleaning/rebuilding did help me resolve another error or two before I got stuck with this current problem. Thanks again...any other ideas? |
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我发现我的时钟分配有问题。修复该问题并重新组织我的时钟缓冲区为我消除了这个错误。
接下来的错误...:smileysurprised: 谢谢! 以上来自于谷歌翻译 以下为原文 I found an issue with my clock assignments. Fixing that problem and reorganizing my clock buffers eliminated this error for me. On to the next error... :smileysurprised: Thanks! |
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好的,抱歉来回。
我一直在努力解决同样的问题。 这是一些更多信息: 基本上,我要做的是替换设计中的XAUI接口。 之前使用XAUI模板使用Rocket I / O核心实现了它。 我现在正试图用XAUI核心/示例设计替换它。 在XAUI示例设计中,差分时钟信号应通过GT11CLK_MGT实例以生成GT11参考时钟(参见UG150的图7-4)。 当我以这种方式编码时,我得到了我最初报告的704错误。 如果我切换回在原始设计中管理差分时钟的方式,则差分信号被传递到IBUFDS以生成参考时钟。 在这种情况下,我得到以下映射错误: 错误:LIT:295 - GT11符号的REFCLK1引脚xaui_if / xaui_block / rocketio_wrapper_i / MGT3只能由GT11CLK的SYNCLK1OUT引脚驱动,或者应保持未连接状态。 ...这似乎表明我必须使用GT11CLK_MGT方法。 再说一次,有没有人有任何建议让我解决这个问题? 谢谢你的时间.... 以上来自于谷歌翻译 以下为原文 Ok, sorry for the back and forth. I've worked myself back around to the same problem. Here is some more info: Basically, what I am trying to do is replace the XAUI interface in the design. It was previously implemented with the Rocket I/O core using the XAUI template. I am now trying to replace that with the XAUI core/example design. In the XAUI example design, the differential clock signal is supposed to pass through a GT11CLK_MGT instance to generate the GT11 reference clock (see Figure 7-4 of UG150). When I code it that way, I get the 704 error that I originally reported here. If I switch back to the way the differential clock was managed in the original design, the differential signal was passed into an IBUFDS to generate the reference clock. In that case, I get the following mapping error: ERROR:LIT:295 - REFCLK1 pin of GT11 symbol xaui_if/xaui_block/rocketio_wrapper_i/MGT3 can only be driven by SYNCLK1OUT pin of a GT11CLK or should be left unconnected. ...which seems to indicate that I have to use the GT11CLK_MGT method. Again, does anyone have any suggestions to get me around this issue? Thanks for your time.... |
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嗨Kratsas,
我已经给你写了一个PM。 我目前与XAUI v9.1和ISE11.3有同样的问题,但到目前为止我无法管理它。 你解决了这个问题吗? 亲切的问候, 托马斯 以上来自于谷歌翻译 以下为原文 Hi Kratsas, I already wrote you a PM. I currently have the same problemwith XAUI v9.1 and ISE11.3, but I couldn't manage it so far. Did you fix the problem? Kind regards, Thomas |
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