在应用时序约束和使用dsport进行模拟时EndBlkPlusV1.9.3出现问题

在Vertex5评估板ML507中使用EndBlkPlus_ForPCIExpress_V1.9对我的设计应用约束时，我遇到了这些问题：（0）首先，我想对由clk信号驱动的所有模块和子模块应用周期约束。
我认为这会给我的设计带来更好的性能。（1）当应用这种类型的时序约束时：“net”signal_name“peroid = 16 ns;”
对于xcf文件或ucf文件，通常会出现错误，指出找不到signal_name。
然后我将“keep”属性添加到signal_name，然后可以找到一些信号，但是即使使用“keep”属性仍然找不到某些信号。
（2）所以我在xst属性中将“keep hierarchy”改为“yes”。
似乎问题已经解决了，约束中的所有信号都被发现了。但是在实现之后，设计从未在模型中模拟200 us时在转录本中显示trn_link_up信息（我知道trn_link_up信息应该显示在
大约90个我们，当然测试从未运行过。（3）我在“生成模拟模型”属性中找到了一个名为“保留层次结构”的选项。
它被检查了，我改变它未经检查。
在模拟时，trn_link_up信息确实显示出来，测试继续进行。
但是有一些时间保持/设置声音。
在模拟之后，在“rx.dat”中，我发现dsport收到的数据包不是它应该拥有的数据包。（4）最后我将“保持层次结构”更改为“否”，并使“保留层次结构”未经检查
然后我删除了所说无法找到的信号的所有约束，并且模拟正确进行。我有这些问题：（1）它是否可以帮助我改善设计的性能，为所有人增加约束
所有模块和子模块的信号？
如果没有，约束应该应用于哪些信号？（2）当“保持层次结构”为“否”时，为什么“保持属性”不能正常工作？（3）为什么在“保持层次结构”时不会显示trn_link_up信息
“in”生成模拟模型“属性被检查？为什么它会在”生成模拟模型“属性中”保留层次结构“属性未选中。我知道”保留层次结构“可以更改”netgen / par“中的”design_name.vhd“文件
/“，但它改变了什么导致模拟失败？（4）由于”保持层次结构“会损害时序性能，在我想要应用的综合和实现时，是否有其他方法可以保持信号名称不变
一个约束？谢谢！
:-)
问候，胡莉



以下为原文

When applying constraints to my design with EndBlkPlus_ForPCIExpress_V1.9 in Vertex5 evaluation board ML507, I confront with those problems:
(0)At first I wanted to apply period constrains to all the modules and submodules driven by a clk signal. I think this would give my design a better performance.
(1)When applying this type of timing constraints : "net "signal_name" peroid = 16 ns;" to xcf file or ucf file, there was usually an error saying signal_name could not be found. And then I added "keep" attribute to signal_name, then some of the signals could be found, but some still could not be found even with "keep" attribute.
(2) So I changed the "keep hierarchy" to "yes" in xst property. And it seemed that the problem had been solved, all the signals in the constraints had been found .But after implemetation, the design never showed the trn_link_up information in transcript when simulating in modelsim for 200 us(I know the trn_link_up information should show up in about 90 us), and of course the test had never run.
(3)And I found a option called "retain hierarchy" in "generate simulation model" property. And it was checked, I changed it unchecked. When simulating, the the trn_link_up information did show up , and the test went on. But then there were some time hold/setup voilations. And after simulation, in "rx.dat" I found the packets the dsport had received was not the packet it should have.
(4)Finally I changed the "keep hierarchy" to "no", and made the "retain hierarchy" unchecked.Then I deleted all the constraints to the signals which were said could not be found, and the simulation went on correctly.

I have these questions:
(1)Whether it can help me to improve the performance of my design to add constraints to all the signals of all the modules and submodules? If not, the constraints should be applied to which signals?
(2)Why "keep attribute" doesn't work well when "keep hierarchy" is "no"?
(3)Why the trn_link_up information will not show up when "retain hierarchy" in "generate simulation model" property is checked?And why it will when "retain hierarchy" in "generate simulation model" property is unchecked.
I know "retain hierarchy" can change the "design_name.vhd" file in "netgen/par/", but what other thing it change leading to make simulation failed?
(4)Since the "keep hierarchy" can hARM the timing performance, is there any other method to keep the signal name unchanged when synthesis and implementaion which I want to apply a constraint to?

Thank you!:-)Regards,
Hu LI