FX3关于最大数据的问题

DMA-Buffy大小与CyfxfxSLIFOFIO-DMAYBUFIUCONTUTP22U U：
DMAiBuffy大小是DMA信道的缓冲区大小正在创建。
CyfFxSLIFOFIO-DMAYBUFICONTUTP22U U是这样的缓冲器的数量分配给DMA信道。
在AN7705中，我们解释了两种通过GPIF接收数据的方案如下：
1。第一个在图10中显示。这里是DMA信道和相关缓冲区的一个生产者和一个消费者套接字。当GPIF接口上没有流量控制机制（没有使用标志）时，存在数据丢失的可能性。
也就是说，我们有4个缓冲区来接收数据。一旦GPIF开始采样数据，将它存放在DMA缓冲区。一旦一个缓冲区已满的GPIF将等到另一个缓冲区可以存储数据。这称为缓冲区切换。这需要大约1微秒。缓冲区切换的发生，另一个处理器连接到GPIF将GPIF写数据，但没有可用的存储缓冲器。如果是这样的话，就会损失数据。
2。二是图11所示。这里是两个生产者和消费者的插座为DMA通道和同事缓冲对于生产各。说，如果你有设置缓冲区的大小为16K和缓冲数到4，然后总的缓冲区的大小分配给这个频道将128KB（16K×4x 2生产者）。在该机制中，我们已经解释过了，而一个缓冲区的一座满是那么GPIF状态机切换到另一个插座。注意插座开关发生在一个时钟周期。这有助于在无延迟和数据丢失的数据接收。
使用最大缓冲区大小增加吞吐量：
让我们用一个较小的缓冲区大小（说，8K和计数为8），FX3设置为接收从外部处理器连接在一个流量控制机制32k GPIF数据块。为32K的每一块，需要4 8k缓冲区。这意味着3的缓冲开关需要接收一个数据块。由于缓冲区转换是一个耗时的过程，外部进程将等待缓冲区可用。
所以如果我们配置DMA与32K，计数2或4。然后缓冲切换发生的每一32k数据块。这是怎样的吞吐量将增加。
                    
                    
               
                                                                                      以下为原文
                                            DMA_BUF_SIZE vs CY_FX_SLFIFO_DMA_BUF_COUNT_P_2_U:
 
 
DMA_BUF_SIZE is the buffer size of the DMA Channel is being created.
 
CY_FX_SLFIFO_DMA_BUF_COUNT_P_2_U is number of such buffers are alloted for the DMA Channel.
 
In AN75705, we have explained two schemes to receive the data through GPIF as follows:
 
1. First one is shown in Diagram 10. Here is one producer and one consumer socket for a DMA Channel and associated buffers. When there is no Flow Control Mechanism over the GPIF interface (No Flags are used), there is a possibility for a data loss.
 
i.e. Say we have 4 buffers to receive the data. Once GPIF starts sampling the data, it will be stored in DMA Buffers. Once one buffer is full the GPIF will wait until another buffer is available to store the data. This is called Buffer Switching. This takes around 1 microsecond. While buffer switching takes place, the another processor connected to GPIF will be writing data to GPIF but there is no buffer available to store. If this is the case, there will be a loss of data.
 
2. Second one is shown in Diagram 11. Here is two producers and one consumer socket for a DMA Channel and associates buffer for a producer each. Say, if you have set Buffer Size to 16K and Buffer Count to 4, then total buffer size allocated for this channel will be 128 KB (16K x 4x 2 producers). In this mechanism, we have explained that while one buffer of one socket is full then the GPIF state machine is switching to another socket. Note that socket switching takes place in one clock cycle. This helps in receiving the data without latency and loss of data.
 
Increasing the throughput using Maximum Buffer size:
 
Let us say we have used a smaller size buffer (say, 8K and count is 8), FX3 is set to receiving some 32K chunks of data from external processor connected over GPIF with a Flow Control Mechanism. For every chunk of 32K, it needs four 8K size buffers. It means 3 buffer switchings are needed to receive one chunk of data. Since buffer switching is a time consuming process, the external process will be waiting for buffer to be available.
 
So if we configure the DMA with 32K, count is 2 or 4. Then the buffer switching takes place for every 32K chunk of data. This is how the throughput will be increasing.
 

SRDR
谢谢你的回答。我知道你在你告诉我an75705。我知道这背后的机制。
但是，使用两个套接字对于提高吞吐量有意义吗？或者在没有流量控制的应用处理器的情况下才有意义。或者换句话说：我有一个流量控制处理器，将使用两个插座产生在这种情况下，更大的吞吐量？
如果我想测试安装固件（例如slavefifosync）两生产插座连接FPGA，它足以改变固件代码：
dmacfg.prodsckid = cy_fx_producer_pport_socket；
dmacfg.conssckid = cy_fx_consumer_u***_socket；
dmacfg.cb = cyfxslfifoptoudmacallback；
<；---我应该插入第二生产插座吗？这足够我用自动DMA模式？或者我是否需要使用multichannelmode？
                    
                    
               
                                                                                      以下为原文
                                            srdr
Thank you for your long answer. I understand you at what you were pointing me in AN75705. I understand the mechanism behind it.
But will the use of two sockets be meaningful for increasing throughput? Or is it just meaningful in the case of application processor without flow control. Or in other words: I have a processor with flow control, will the use of two sockets generate more throughput in this case?
 
If I want to test the setup firmware (e.g. SlaveFiFoSync) with tow producer sockets with attached FPGA, is it enough to change this code in firmware:
 
    dmaCfg.prodSckId = CY_FX_PRODUCER_PPORT_SOCKET;  
    dmaCfg.consSckId = CY_FX_CONSUMER_USB_SOCKET;
    dmaCfg.cb = CyFxSlFifoPtoUDmaCallback;
 
  <--- Should I just insert a second producer socket in here? Is it enough when I use auto dma mode? Or do I need to use multichannelmode?

当您与两个生产商套接字和一个带有套接字交换机制的消费者相比，在AN6997中执行的流量控制实现时，吞吐量将增加。
如果您在AN779中执行多通道到一通道的实现，则无法访问不同端点的数据。
如果要使用多个到一个通道发送不同端点的数据，则需要修改GPIF状态机。这需要来自FPGA的附加控制线来切换套接字。
是的，在创建DMA通道时，必须插入生产者套接字。
我可以看到，您已经在这个线程中提到的文件中进行了修改。
请注意，即使在这一点上，您也需要更改GPIF状态机。
                    
                    
               
                                                                                      以下为原文
                                            The throughput will increase when you go with two producer sockets and one consumer with socket switching mechanism compared to flow control implementation done in AN65974.
 
If you go with many to one channel implementation done in AN75779, you do not have access to send data over different endpoints.
 
If you want to send data over different endpoints using Many to one Channel, you need to modify the GPIF state machine. This requires additional control lines from FPGA to switch the sockets.
 
Yes, you have to insert producer socket while creating the DMA Channel.
 
I can see that you have done this modification in files mentioned in thisthread.
 
Note that even in this, you need to change the GPIF State machine.

亲爱的SRDR，
我只想要两个插座的一个端点（P2U-转移）我不得不修改GPIF状态机在slavefifosync？我需要从FPGA FX3开关插座附加控制线？
赛普拉斯提供UVC例子与例子中集成GPIF状态机。在设置状态机有两种状态push_data_sck0和sck1交换机或者当缓冲区数目得到充分。
但在slavefifosync UVC的例子比较不需要地址线，而是thread_0和thread_1选择在国。
我需要帮助实现这一点。也许我们可以通过电子邮件进行这件事？在slavefifosync只有一个端点和2个线程，我甚至不能得到一个端点项目的工作slavefifosync。
GPIF.PNG
42.2 K
                    
                    
               
                                                                                      以下为原文
                                            Dear srdr,
I only want one endpoint with two sockets (P2U transfer) Do I then have to modifiy the GPIF state machine in SlaveFifoSync ? Do I then need additional control lines from fpga to FX3 to switch the sockets?
 
Cypress provided the UVC example with the in the example integrated GPIF state machine. In the provided state machine there are two states PUSH_DATA_SCK0 and SCK1 which switch alternatively when buffer count gets full.
 
But in comparison to SlaveFifoSync the uvc example does not need a address line but rather the thread_0 and thread_1 selection is made inside the states.
 
I need help implementing this. Perhaps we can go through this with email? In SlaveFiFoSync with only one endpoint and SlaveFifoSync with 2 Sockets this Thread I cannot even get the one endpoint project to work.

   

        

•                                         gpif.png                42.2 K            
     
  

如果UVC，传感器或FPGA将提供抗体，LV，PCLK时钟和数据线。我们用LV，FV和GPIF计数器开关插座内两生产插座中。
如果你可以在类似的方式提供的控制线，您可以使用UVC应用笔记an75779 GPIF状态机。否则，请通过与Slave FIFO an65974 GPIF状态机。
否则，你甚至可以写一个自定义的状态机根据您的要求。
请让我知道以下细节：
在你的情况下，预期的吞吐量是多少？
你的申请是什么？
FPGA的界面是什么？
                    
                    
               
                                                                                      以下为原文
                                            In case of UVC, the sensor or FPGA will be providing the FV, LV, PCLK and data lines. We have used the LV, FV and internal GPIF counters to switch the sockets among two producer sockets.
 
If you can provide the control lines in the similar way, you can use the UVC App Note AN75779 GPIF State Machine. Else, please go through with Slave FIFO AN65974 GPIF State machine.
 
Otherwise, you can even write a custom state machine as per your requirement.
 
Please let me know the following details:
 
What is the expected throughput in your case?
What is your application?
What is the interface of FPGA here?