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关于FX3配置FPGA的8868问题
1)在AN848 68中,如果FPGA已经由FX3配置,它将切换到从FIFO模式。这是否意味着原来的代码只能配置FPGA一次?是否有可能拆分通道,一个通道只用于配置。如果该信道从主机获得数据,则意味着配置是预期的,并且FX3GPIO切换到配置。 2)如果主机没有在AN848 68发送数据到FX3,那么GPIO引脚是否是三态的? 3)将GPIO引脚将三态当RESET引脚保持活跃。 以上的问题来自我的新计划:配置kintex-7 FPGA大师BPI模式供电然后FX3可以重新配置FPGA只要主机发送配置数据,FX3还应该在Slave FIFO模式使FPGA与主机之间的数据传输在不配置tion. BPI和FX3 SPI将共享一些FPGA引脚。如何避免冲突? 谢谢您。 以上来自于百度翻译 以下为原文 My questions on AN84868 configuring FPGA by FX3 1) In AN84868, if the FPGA has been configured by FX3, it will switch to slave FIFO mode. Does this mean the original codes can only configure FPGA for once? Is it possible to split channels, one channel is only for configuring. If this channel get the data from host, it means the configuration is expected,and the FX3 GPIO switch to configuration. 2) If the host have not send data to FX3 in AN84868, will the GPIO pins be tristate? 3) Will the GPIO pins be tristate when the reset pin is hold active. The above questions come from my new plan: configuring kintex-7 FPGA by Master BPI mode on powering up and then FX3 can reconfigure FPGA as long as the host sends configuring data, the FX3 should also be in a slave FIFO mode to enable the transfer of data between FPGA and host when not in configuration. BPI and FX3 SPI will share some of FPGA pins. How to avoid conflict? Thank you. |
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7个回答
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你好,Maverick Xiang,
FPGA为bin文件可以在附加效用不止一次发。但是,对FPGA进行配置,配置数据必须放在复位发送到FPGA。这可以做一个GPIO引脚连接到FPGA的重置和驱动方法。 在FX3装置上电复位后三态的GPIO引脚默认状态。 - FX3 SPI写入数据到FPGA只有当宿主应用程序发送命令。只有在这种情况下,芯片选择(CS #)引脚FPGA的SPI驱动的FX3。所以,不会有冲突,BPI和FX3 SPI。 请让我知道如果你有疑问。 最好的问候, 斯里纳斯 以上来自于百度翻译 以下为原文 Hello Maverick Xiang, - The bin file for the FPGA can be sent over the attached utility more than once. But, for the FPGA to be configured, the configuration data has to be sent to FPGA by holding it in RESET. This can be done connecting a GPIO pin to the FPGA RESET and driving the same. - The default state of the GPIO pins after the FX3 device is powered up and after reset is tristate. - FX3 SPI writes data to the FPGA only when the host application sends the command. Only under this condition, the Chip Select (CS#) pin of the FPGA is driven by the FX3 SPI. So, there will not be a conflict between the BPI and FX3 SPI. Please let know if you have further queries. Best regards, Srinath S |
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wangcong12138 发表于 2018-9-3 08:13 Srinath,谢谢你。 据我所知,Xilinx FPGA没有复位引脚。您是指用户定义的FPGA复位引脚吗?为什么我要保持这个引脚激活?在AN848 68中,FX3首先配置它的GPIO来配置FPGA,然后切换到FIFO传输模式。为什么它可以配置FPGA多少次?我知道,如果FX3被重置,它可以再次配置FPGA,因为固件被刷新。如果FX3没有重置,它是否能够配置FPGA一次? 在an84868,我没有看到一个CS引脚GPIO SPI。在FPGA CS #是BPI配置输出。在FPGA中,从属串行操作中不存在附加的CS ^πPIN。 将FX3 SPI引脚保持三态,如果没有数据从主机发送? 谢谢您。 以上来自于百度翻译 以下为原文 Srinath, thank you. As to my knowledge, Xilinx FPGA do not have a RESET pin. Do you mean user defined FPGA RESET pin? Why should I hold this pin active? In AN84868, FX3 first configures its GPIO to configure FPGA, then switches to FIFO transfer mode. Why it can configure FPGA many times? I understand that if FX3 is reset, it can configure FPGA once more, because the firmware is refreshed. If FX3 is not reset, is it able to configure FPGA one more time? In AN84868, I do not see a CS pin in SPI GPIO. In FPGA CS# is an output for BPI configuration. No additinal CS# pin exists in FPGA for Slave Serial operation. Will the SPI pin for FX3 stay tristated if no data are sent from the host? Thank you. |
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邱艳yyxx 发表于 2018-9-3 08:30 你好,Maverick Xiang, 在应用笔记中提到的Xilinx FPGA可重新配置的过程,program_b引脚被拉低500ns或更长。 -配置过程后,FX3开关FIFO传输模式中,应用笔记固件不初始化SPI模块重新配置IO矩阵。因此,FX3不能用于重新配置过程。但是,固件可以被修改,SPI块保留而不去初始化和配置可近的供应商的命令。 通过CS #引脚,我指的是SSN(从选择)引脚的FX3 SPI模块。此引脚将三态当设备没有解决。 最好的问候, 斯里纳斯 以上来自于百度翻译 以下为原文 Hello Maverick Xiang, - The Xilinx FPGA mentioned in the app note can be made to restart its configuration process when the PROGRAM_B pin is pulled LOW for 500ns or longer. - After the configuration process, the FX3 switches to FIFO transfer mode during which the App Note firmware de-initializes the SPI block to re-configure the IO matrix. Hence, the FX3 cannot be used to resend the configuration process. But, the firmware can be modified such that the SPI block is retained without de-initialization and the configuration can be resent over the vendor command. - By CS# pin, I meant the SSN (Slave Select) pin of the FX3 SPI block. This pin will be tri-stated when the device is not addressed. Best regards, Srinath S |
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wangcong12138 发表于 2018-9-3 08:42 在FX3,如果spi_ssn不是断言,将spi_mosi和SPI时钟是三态?如果主机不发送配置数据,将spi_ssn和其他两引脚是三态本应用笔记? 以上来自于百度翻译 以下为原文 In FX3, if SPI_SSN is not asserted, will SPI_MOSI and SPI CLOCK be tristated? If the host does not send configuration data, will SPI_SSN and the other 2 pins be tristated in this application note? |
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邱艳yyxx 发表于 2018-9-3 08:57 你好,Maverick Xiang, -当SPIXSSN未被断言时,MOSI线将被三态化,SPI时钟(SCLK)线将处于空闲状态。 -在APP注释示例中,在完成配置过程之后,对SPI块进行去初始化,并将GPIF总线宽度设置为从FIFO操作的32位。 最好的问候, 斯里纳斯 以上来自于百度翻译 以下为原文 Hello Maverick Xiang, - When the SPI_SSN is not asserted, the MOSI line will be tri-stated and the SPI CLOCK (SCLK) line will be in its IDLE state. - In the App Note example, after the configuration process is done, the SPI block is de-initialized and the GPIF bus width is set to 32 bit for the slave FIFO operation. Best regards, Srinath S |
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wangcong12138 发表于 2018-9-3 09:17 谢谢您。有没有任何证据证明你的答案“当SPIXSSN没有被断言,MoSI线将被三次声明”,在这个应用笔记中,这不是真的,因为SSN必须断言和去断言,然后将数据发送给从FPGA的合适的FPGA配置。 SCK的空闲状态没有被改变? 以上来自于百度翻译 以下为原文 Thank you. Is there any proof of your answer “When the SPI_SSN is not asserted, the MOSI line will be tri-stated", in this application note,it is not the truth,because ssn must be asserted and deasserted before sending data to slave FPGA for a proper FPGA configuration. The idle state of sck is not tristated? |
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邱艳yyxx 发表于 2018-9-3 09:26 你好,Maverick Xiang, -混乱道歉。一般来说,在一个SPI传输,如果SSN线去断言,数据线是不是驱动/主采样。但是,在应用笔记例如固件的情况下,对FX3 SPI块只用于将数据发送到FPGA。对FX3的spi_ssn线连接到FPGA的program_b销。此引脚用于异步复位的FPGA和活性低。因此,对FX3的spi_ssn线拉低,然后释放高以程序的配置数据的FPGA。在这种情况下,MOSI线驱动的数据时,spi_ssn线高(的主张)。 - SCK的空闲状态取决于时钟极性。在应用笔记的例子,时钟极性设置为CyTrue因此SCK的空闲状态是逻辑高。 最好的问候, 斯里纳斯 以上来自于百度翻译 以下为原文 Hello Maverick Xiang, - Apologies for the confusion. In general, in an SPI transfer, if the SSN line is de-asserted, the data lines are not driven/sampled by the master. But, in case of the app note example firmware, the SPI block of FX3 is only used to serialize the data to be sent over to FPGA. The SPI_SSN line of FX3 is connected to the PROGRAM_B pin of FPGA. This pin is used to asynchronously reset the FPGA and is active LOW. So, the SPI_SSN line of the FX3 is pulled LOW and then released HIGH so as to program the FPGA with the configuration data. In this case, MOSI line is driven with the data when the SPI_SSN line is HIGH (de-asserted). - The idle state of SCK depends on the CPOL. In the app note example, CPOL is set to CyTrue and hence the idle state of SCK is logic HIGH. Best regards, Srinath S |
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