求教关于MSP432P401R LaunchPad的几个问题

我看的文档就是你说的那个user guide。不仅是MSP432这款产品的这两个寄存器没有说明如何使用，MSP430x5xx and MSP430x5xx family user's guide 也没有对eUSCI模块下I2C模式这两个寄存器的使用方法进行说明。

参见 P779 MSP432 用户手册, 
I2C Clock Generation and Synchronization
The I2C clock SCL is provided by the master on the I2C bus. When the eUSCI_B is in master mode,
BITCLK is provided by the eUSCI_B bit clock generator and the clock source is selected with the
UCSSELx bits. In slave mode, the bit clock generator is not used and the UCSSELx bits are don't care.
The 16-bit value of UCBRx in registers UCBxBR1 and UCBxBR0 is the division factor of the eUSCI_B
clock source, BRCLK. The maximum bit clock that can be used in single master mode is fBRCLK/4. In multimaster
mode, the maximum bit clock is fBRCLK/8. The BITCLK frequency is given by:
fBitClock = fBRCLK/UCBRx
The minimum high and low periods of the generated SCL are:
tLOW,MIN = tHIGH,MIN = (UCBRx/2)/fBRCLK when UCBRx is even
tLOW,MIN = tHIGH,MIN = ((UCBRx – 1)/2)/fBRCLK when UCBRx is odd
The eUSCI_B clock source frequency and the prescaler setting UCBRx must to be chosen such that the
minimum low and high period times of the I2C specification are met.
During the arbitration procedure the clocks from the different masters must be synchronized. A device that
first generates a low period on SCL overrules the other devices, forcing them to start their own low
periods. SCL is then held low by the device with the longest low period. The other devices must wait for
SCL to be released before starting their high periods. Figure 24-16 shows the clock synchronization. This
allows a slow slave to slow down a fast master.

在MSPWare中有一个工程     msp432p401_euscib0_i2c_10。在这个工程里有这么句话
 UCB0BRW = 0x0018;                       // baudrate = SMCLK / 8
为什么是8分频而不是24分频。
另外，这个SMCLK并没有被配置过，它的默认值是4MHz吗？？如果我自己配置了SMCLK，在之后要如何变回默认值？
（新手，问的问题有点白，还请见谅）