为什么BUFG到DCM时钟定时错误？

要做的第一件事是检查翻译消息，看看是否由于某种原因你的约束被忽略了。
顺便说一句，错误消息将约束括在尖括号中，但那些不应该进入UCF文件。
约束应如下所示：NET“sensor_video_1_iClock_pin”CLOCK_DEDICATED_ROUTE = FALSE
谢谢和RegardsBalkrishan -----------------------------------------------
---------------------------------------------请将帖子标记为
一个答案“接受为解决方案”，以防它有助于解决您的查询。如果一个帖子引导到解决方案，请给予赞誉。



以下为原文

The first thing to do is check the translate messages to see if for some reason your constraint has been ignored.  By the way, the error message encloses the constraint in angle brackets, < ... >, but those should not go into the UCF file.  The constraint should look like:



NET "sensor_video_1_iClock_pin" CLOCK_DEDICATED_ROUTE = FALSEThanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.

不幸的是，这个问题没有给出合适的答案。
我不想摆脱将其降级为警告的错误，我想实际使用时钟资源，实际上我们希望保留DEDICATED_ROUTE =“TRUE”
我已经修改了设计以遵循以下路径： 
- >面料 
|
GCLK> BUFIO2> BUFG> SerDes 
| 
- > DCM> Fabric
这已经清除了错误，但是当BUFG（UG382 p32）之后的Fabric DIVCLK点击然后用于T触发器（在这种情况下为negedge SERDES_DIVCLK）时，已经创建了类似的DEDICATED_ROUTE =“FALSE”问题，报告了
BUFG之后的网络无法使用专用时钟分配，即将DIVCLK线路进入SerDes模块关闭专用路由。
干杯。
埃德



以下为原文

Unfortunatly that didn't really give a suitable answer to the issue. I don't want to get rid of the error downgrading it to a warning, I want to actually use the clock resources, in effect we are looking to retain DEDICATED_ROUTE = "TRUE"
 
I've since modified the design to follow the path:
    
                                                -> Fabric
                                               |
GCLK > BUFIO2 > BUFG > SerDes
                               |
                               -> DCM > Fabric
 
This has now cleared the error, but has created a similar DEDICATED_ROUTE = "FALSE" problem when the Fabric DIVCLK tap after the BUFG (UG382 p32) is then used in a T Flip-Flop (in this case negedge SERDES_DIVCLK), reporting that the net after the BUFG cannot use dedicated clock distribution, i.e. taking the DIVCLK line going into the SerDes blocks off the dedicated routing.
 
Cheers.
Ed
 
 

E，
简单的问题：你不能从这里到达那里。
DCM输入必须来自IBUFG，BUFG或常规互连。
我还将GCLK放在BUFG上，以便能够到达DCM。
只有这么多方法允许客户路由。
你拥有的那个不存在。
Austin Lesea主要工程师Xilinx San Jose



以下为原文

e,
 
Simple problem:  you cannot get there from here.  DCM input must come from an IBUFG, BUFG, or over regular interconnect.
 
I would also put the GCLK on a BUFG so it is able to reach the DCM.

Only so many ways to allow a customer to route.  The one you have doesn't exist.
 
 
Austin Lesea
Principal Engineer
Xilinx San Jose