如何锁定DCM

DCM在开机时不会被锁定，因此您的分配将导致它永远不会从重置中释放。
使用状态机检测失锁，在适当的时间内置位复位，然后暂停一段时间以使DCM有时间获取锁定。



以下为原文

The DCM will not be locked at power on, so your assignment will cause it to never be released from reset.
 
Use a state machine to detect loss of lock, assert reset for the appropriate amount of time, then hold off for a while to give the DCM time to acquire the lock.

谢谢
使用状态机检测失锁，断言重置
适当的时间，然后暂缓一段时间给DCM
获得锁定的时间。
我用过
总是@（posedge CLKFX）开始lock_shift如果（lock_shift == 4'b1111）开始lock_real
高电平有效RST引脚必须连接到动态信号或必须接地。
RST输入必须置位三个有效CLKIN周期或更长时间。
因此有必要将RESET作为外部输入（接地），我是否正确？
如何使用RESET for DCM和其余逻辑？
任何帮助，将不胜感激？
问候
费萨尔



以下为原文

Thanks
 
Use a state machine to detect loss of lock, assert reset for the appropriate amount of time, then hold off for a while to give the DCM time to acquire the lock.
 
I have used as
 
always@(posedge CLKFX)
begin
    lock_shift <= {lock_shift[2:0], LOCKED};
        if(lock_shift == 4'b1111)
                begin
                lock_real <= 1'b1; // DCM stable
                end
        else
                begin
                lock_real <= 1'b0; // Unstable
                end
end
 
 
In this i did not use  any external RESET . What I did is
 
rst_reg=1'b0;
assign RESET = rst_reg;
 
Did I miss anything ?
 
From the datasheet
 
If the DCM loses lock—i.e., the LOCKED output was High then goes Low—then the FPGA
application must assert RST to force the DCM to reacquire the input clock frequency.

The active-High RST pin either must connect to a dynamic signal or must be
tied to ground. The RST input must be asserted for three valid CLKIN cycles or longer.
 
 
So it is necessary to have a RESET as external input (ground) , Am I correct ?
 
How to use the RESET for DCM and rest of the logic ?
 
Any help would be appreciated?
 
Regards
 
Faisal
 
 

我认为断言RESET输入会导致时钟输出停止，并导致LOCK输出被置低。
如果您依靠PLL或DCM时钟输出来同步清除RESET信号，则可能需要等待很长时间。
我对正确使用RESET输入到PLL或DCM的理解是： 
当LOCK因CLOCK输入中断或干扰而丢失时，在输入CLOCK重新建立并稳定后，短暂置位RESET以复位内部LOCK电路。
这将加速重新获取LOCK到新的输入时钟。
- 鲍勃埃尔金德
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以下为原文

I believe that asserting RESET input causes clock outputs to halt, and causes LOCK output to be de-asserted.
If you are relying on PLL or DCM clock outputs to synchronously clear the RESET signal, you might be waiting a very long time.
 
My understanding of the proper use of RESET input to PLL or DCM is:

when LOCK has been lost due to CLOCK input interruption or disturbance, assert RESET briefly to reset the internal LOCK circuitry after the input CLOCK has been re-established and stabilised.  This will speed up re-acquisition of LOCK to the new input clock.

- Bob Elkind
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pfaisalbe写道：
因此有必要将RESET作为外部输入（接地），我是否正确？
在那段代码中，您根本没有重置DCM。
手册说你必须将RST连接到动态控制信号（状态机或其他东西）或接地（如果你不想打扰它，也许你的输入时钟非常稳定）。
只要输入时钟良好，您的代码就可以正常工作。
也许其他人可以评论是否依赖任何DCM永远锁定是一个好主意？
我想它不是。
DS162规定，LOCK_DLL是DCM获取锁定所需的最长时间，为5 ms，因此您的逻辑必须至少在重置之间暂停一段时间，否则它有可能无法锁定。



以下为原文

 

pfaisalbe wrote:
[size=11.8056px] 
So it is necessary to have a RESET as external input (ground) , Am I correct ?
 

In that piece of code, you didn't reset the DCM at all. The manual says you have to connect RST to a dynamic control signal (a state machine, or something else) OR ground (if you don't want to bother with resetting it, perhaps if your input clock is very stable). Your code should work, as long as your input clock is good. Maybe someone else can comment on whether it's a good idea to ever rely on any DCM remaining locked forever? I imagine it's not.
 
DS162 states that LOCK_DLL, the maximum time that the DCM can take to acquire a lock, is 5 ms, so your logic must pause for at least this amount of time between resets or else there's a chance it won't ever lock.