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[问答]

这是使用DCM的正确方法吗?

wire CLKIN_IBUFG;
线CLK0_BUF;
导线LOCKED_OUT;导线tx_clk_0;
wire tx_clk_1;
//输入到DCMBUFG BUFG_INST_0(.I(tx_clk_0),. O(CLKIN_IBUFG));
//来自具有LOCKED控制的DCM的输出BUFGCE BUFGCE_INST_0(.O(tx_clk_1),. CE(LOCKED_OUT),. I(CLK0_BUF));
DCM_SP#(。CLK_FEEDBACK(“1X”),. CLKDV_DIVIDE(2.0),. CLKFX_DIVIDE(1),. CLKFX_MULtiPLY(4),. CLKIN_DIVIDE_BY_2(“FALSE”),. CLKIN_PERIOD(62.500),. CLKOUT_PHASE_SHIFT(“FIXED”)
,.DESKEW_ADJUST(“SYSTEM_SYNCHRONOUS”),. DFS_FREQUENCY_MODE(“LOW”),. DLL_FREQUENCY_MODE(“LOW”),. DUTY_CYCLE_CORRECTION(“TRUE”),.FACTORY_JF(16'hC080),。PHASE_SHIFT(192),. STARTUP_WAIT(
“FALSE”))DCM_SP_INST(.CLKFB(tx_clk_1),. CLKIN(CLKIN_IBUFG),. DSSEN(0),. PSCLK(0),. PSEN(0),. PSINCDEC(0),. RST(hw_or_sw_reset),.
CLKDV(),. CLKFX(),. CLKFX180(),. CLK0(CLK0_BUF),. CLK2X(),. CLK2X180(),. CLK90(),. CLK180(),. CLK270(),. LOCKED(LOCKED_OUT)
,.PSDONE(),. STATUS());
我正在尝试生成输入时钟的延迟版本。
预期的延迟是270度。
但它似乎不适用于我的董事会。
有人可以告诉我这是否是使用DCM的正确方法?
我不确定我是否在输出缓冲区(BUFGCE)上做得对。
如果这是DCM的正确方法,那么我可以查看我设计的其他部分,以找出问题所在。
谢谢

以上来自于谷歌翻译


以下为原文

wire CLKIN_IBUFG;
wire CLK0_BUF;
wire LOCKED_OUT;
wire tx_clk_0;
wire tx_clk_1;

//input to the DCM
BUFG BUFG_INST_0 (.I(tx_clk_0),
.O(CLKIN_IBUFG));

//output from the DCM with LOCKED control
BUFGCE BUFGCE_INST_0 (
.O (tx_clk_1),
.CE (LOCKED_OUT),
.I (CLK0_BUF));

DCM_SP #( .CLK_FEEDBACK("1X"), .CLKDV_DIVIDE(2.0), .CLKFX_DIVIDE(1),
.CLKFX_MULTIPLY(4), .CLKIN_DIVIDE_BY_2("FALSE"),
.CLKIN_PERIOD(62.500), .CLKOUT_PHASE_SHIFT("FIXED"),
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), .DFS_FREQUENCY_MODE("LOW"),
.DLL_FREQUENCY_MODE("LOW"), .DUTY_CYCLE_CORRECTION("TRUE"),
.FACTORY_JF(16'hC080), .PHASE_SHIFT(192), .STARTUP_WAIT("FALSE") )
DCM_SP_INST
(
.CLKFB(tx_clk_1),
.CLKIN(CLKIN_IBUFG),
.DSSEN(0),
.PSCLK(0),
.PSEN(0),
.PSINCDEC(0),
.RST(hw_or_sw_reset),
.CLKDV(),
.CLKFX(),
.CLKFX180(),
.CLK0(CLK0_BUF),
.CLK2X(),
.CLK2X180(),
.CLK90(),
.CLK180(),
.CLK270(),
.LOCKED(LOCKED_OUT),
.PSDONE(),
.STATUS());

I am trying to generate a delayed version of input clock. The intended delay is 270 degree. But it doesn't seem to work on my board. Could someone tell me if this is the right way of using DCM? I am not sure if I did it right on the output buffer  (BUFGCE). If this is the right way of DCM than I can look into other part of my design to figure out what goes wrong.

Thanks

回帖(5)

刘丰标

2019-3-25 14:10:16
如果你想要相移270度而不是使用输出时钟.CLK270。
--Krishna

以上来自于谷歌翻译


以下为原文

if you want phase shift of 270 degree than use the output clock .CLK270.
 
--Krishna
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李云

2019-3-25 14:21:06
我知道。
但我问输出缓冲区是否正确?
我应该以这种方式使用LOCKED引脚吗?
并且应该来自CLK0或CLK270的反馈

以上来自于谷歌翻译


以下为原文

I know. But I am asking about the output buffer whether or not it's correct? Should I use LOCKED pin in this way? And should the feedback from CLK0 or CLK270
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黄淳

2019-3-25 14:40:19
qizhong19920114写道:
我知道。
但我问输出缓冲区是否正确?
我应该以这种方式使用LOCKED引脚吗?
并且应该来自CLK0或CLK270的反馈
反馈必须来自CLK0,否则,CLK270输出将与CLKIN输入对齐,您将无法获得所需的延迟。
我从未见过有人使用DCM锁定信号来禁用时钟(在BUFGCE上),但我想你可以做到。
在DCM锁定之前,tx_clk_1网络上有什么东西不能容忍虚假时钟吗?
最好使用DCM锁定条件为该下游逻辑生成复位。
----------------------------是的,我这样做是为了谋生。

以上来自于谷歌翻译


以下为原文

qizhong19920114 wrote:
I know. But I am asking about the output buffer whether or not it's correct? Should I use LOCKED pin in this way? And should the feedback from CLK0 or CLK270
The feedback has to come from CLK0 because otherwise, the CLK270 output will line up with the CLKIN input and you won't get the delay you want.
 
I've never seen anyone use the DCM locked signal to disable a clock (on the BUFGCE) but I suppose you could do it. Is there anything on that tx_clk_1 net that can't tolerate spurious clocks until the DCM locks? It's probably better to use the DCM locked condition to generate a reset for that downstream logic.
----------------------------Yes, I do this for a living.
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李云

2019-3-25 14:51:08
嗨,我不知道下游逻辑的容差是多少。
你的意思是我应该使用DCM锁作为下游逻辑的重置吗?
但我已经为下游逻辑重置了一次。
我探测LOCKED引脚的输出,它总是很低,尽管可以从示波器观察到输入DCM的时钟是一致的。
为什么LOCKED引脚总是很低?
我的设计有什么问题吗?

以上来自于谷歌翻译


以下为原文

Hi, I don't know what is the tolerance of the downstream logic. Do you mean I should use the DCM lock as the reset for the downstream logic? But I already have a reset for the downstream logic. I probe the output of LOCKED pin and it's always low although the clock fed into the DCM can be observed from the oscilloscope is consistant. Why is LOCKED pin always low? Did I do anything wrong with the design? 
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