赛灵思
直播中

张峰

8年用户 195经验值
私信 关注
[问答]

LUT和FF在一个单独的切片中

嗨,
是否有全局实现指令(属性)会强制实现工具将LUT和FF放在单独的片中(对FF或LUT使用单个片)?
这是非理想的,也是我所知道的资源浪费......但我正在开发耐辐射设计,并且希望将FPGA的所有组件分开并彼此远离...

以上来自于谷歌翻译


以下为原文

Hi,
Is there a global implementation directive (attribute) that would force implemenatation tool to place LUT and FF in a separate slice (use a single slice either for FF or LUT) ?
This is nonoptimal and kind of waste of resources I know ... but I'm developing radiation tolerant design and would like to keep all the components of FPGA separately and away from each other ...

回帖(1)

潘晶燕

2018-10-29 12:07:55
男,
从不高兴的角度来看,这样做无益。
任何增加关键配置位数的策略都会使横截面变得更糟。
分离资源会增加电线,这极大地增加了破坏设计的配置位。
去过也做过。
馊主意。
不要浪费你的时间。
SEM IP是我们对烦恼的回答。
如果这是空间应用程序,由于美国国务院的贸易限制,论坛中不会考虑这些因素:您必须联系您的A / D支持。
Austin Lesea主要工程师Xilinx San Jose

以上来自于谷歌翻译


以下为原文

m,
 
There is zero benefit from doing this from an upset perspective.  Any strategy that increases the number of critical configuration bits makes the cross section worse.  Separating resouces adds wires, which enormously increases config bits that break the design.
 
Been there, done that.  Bad idea.  Do not waste your time.
 
The SEM IP is our answer to upsets.

If this is a space application, those are not considered here in the forums due to US State Department trade restrictions:  you must contact your A/D support.
Austin Lesea
Principal Engineer
Xilinx San Jose
举报

更多回帖

发帖
×
20
完善资料,
赚取积分