赛灵思
直播中

杨杰

7年用户 1107经验值
私信 关注
[问答]

用户具有过度约束的组件ioclk_buf

我在使用我的斯巴达6xc6slx45-3csg324 FPGA进行映射时出现以下错误。
“错误：位置：1318： - 用户具有过度约束的组件ioclk_buf。没有可放置的站点满足用户约束。请查看驱动程序组件的用户约束和ioclk_buf的加载组件。
错误：打包：1654： - 时序驱动的放置阶段遇到错误。“
ioclk_buf是BUFPLL原语的对象，我用它来生成高速IO时钟（主时钟的一半）。
下面是我的设计的ucf文件，我想在我的Atlys主板上使用HDMI端口同时在两个屏幕上显示彩条。
我的设计的顶级模块也附加。
我对这个问题的看法是由于bufpll（ioclk_buf）的不正确的布局规划。
############################################为不同的SP601板设置VCCAUX
############################################ VCCAUX = 3.3;
#########################################重置按钮和LED #####
################################### NET“RSTBTN”LOC =“N4”; NET“LED”LOC
=“H12”; NET“LED”LOC =“G13”; NET“LED”LOC =“E16”; NET“LED”LOC =“E18”;
##################################################
############################# SYSCLK输入###################
##################################################
######### NET“SYS_CLK”LOC =“L15”;
##################################################
#############################机械开关（SW）################
##################################################
############ NET“SW”LOC =“A10”| IOSTANDARD = LVCMOS33; NET“SW”LOC =“D14”| IOSTANDARD = LVCMOS33; NET“SW”LOC =“C14”|
IOSTANDARD = LVCMOS33; NET“SW”LOC =“P15”| IOSTANDARD = LVCMOS33;
##################################################
#############################调试端口＃JA1 #################
##################################################
########### NET“DEBUG [0]”LOC =“B12”| IOSTANDARD = LVCMOS33; NET“DEBUG [1]”LOC =“B11”| IOSTANDARD = LVCMOS33;
##################################################
############################# DCM / PLL / BUFPLL职位###############
##################################################
############## INST“PCLK_GEN_INST”LOC =“DCM_X0Y3”;
#INST “PLL_OSERDES” LOC = “PLL_ADV_X0Y1”;＃INST “ioclk_buf” LOC = “BUFPLL_X1Y0”; ############################
################时间约束################################
########### NET “clk50m_bufg” TNM_NET = “TNM_CLK50M”; tiMESPEC “TS_CLK50M”= PERIOD “TNM_CLK50M” 50兆赫HIGH 50％优先级0;
NET“pclk”TNM_NET =“TNM_PCLK”; TIMESPEC“TS_PCLK”= PERIOD“TNM_PCLK”108 MHz HIGH 50％PRIORITY 0;
NET“pclkx2”TNM_NET =“TNM_PCLKX2”; TIMESPEC“TS_PCLKX2”= PERIOD“TNM_PCLKX2”TS_PCLK * 2;
NET“pclkx10”TNM_NET =“TNM_PCLKX10”; TIMESPEC“TS_PCLKX10”= PERIOD“TNM_PCLKX10”TS_PCLK * 10;
##多循环路径#TIMEGRP“bramgrp”= RAMS（enc0 / pixel2x / dataint）;
TIMEGRP“fddbgrp”= FFS（enc0 / pixel2x / db）; TIMEGRP“bramra”= FFS（enc0 / pixel2x / ra）;
TIMEGRP“bramgrp”= RAMS（enc1 / pixel2x / dataint）;
TIMEGRP“fddbgrp”= FFS（enc1 / pixel2x / db）; TIMEGRP“bramra”= FFS（enc1 / pixel2x / ra）;
TIMESPEC“TS_ramdo”=从“bramgrp”到“fddbgrp”TS_PCLK; TIMESPEC“TS_ramra”=从“bramra”到“fddbgrp”TS_PCLK;
顶部###########################
############ NET“TMDS2（0）”LOC =“R3”| IOSTANDARD = TMDS_33;
#BlueNET“TMDSB2（0）”LOC =“T3”| IOSTANDARD = TMDS_33; NET“TMDS2（1）”LOC =“T4”| IOSTANDARD = TMDS_33;
#RedNET“TMDSB2（1）”LOC =“V4”| IOSTANDARD = TMDS_33; NET“TMDS2（2）”LOC =“N5”| IOSTANDARD = TMDS_33;
#GreenNET“TMDSB2（2）”LOC =“P6”| IOSTANDARD = TMDS_33; NET“TMDS2（3）”LOC =“T9”| IOSTANDARD = TMDS_33;
＃ClockNET“TMDSB2（3）”LOC =“V9”| IOSTANDARD = TMDS_33;
NET“TMDS1（0）”LOC =“D8”| IOSTANDARD = TMDS_33;
#BlueNET“TMDSB1（0）”LOC =“C8”| IOSTANDARD = TMDS_33; NET“TMDS1（1）”LOC =“C7”| IOSTANDARD = TMDS_33;
#RedNET“TMDSB1（1）”LOC =“A7”| IOSTANDARD = TMDS_33; NET“TMDS1（2）”LOC =“B8”| IOSTANDARD = TMDS_33;
#GreenNET“TMDSB1（2）”LOC =“A8”| IOSTANDARD = TMDS_33; NET“TMDS1（3）”LOC =“B6”| IOSTANDARD = TMDS_33;
＃ClockNET“TMDSB1（3）”LOC =“A6”| IOSTANDARD = TMDS_33;
请帮我解决这个问题。
谢谢
vtc_demo.v 21 KB

以上来自于谷歌翻译


以下为原文

I am getting the following error on mapping with my spartan 6 xc6slx45-3csg324 fpga.

"ERROR:Place:1318: - User has over-constrained component ioclk_buf. There are no placeable sites that satisfy the user constraints. Please review the user constraints on the driver component and the load components of ioclk_buf.

ERROR:Pack:1654: - The timing-driven placement phase encountered an error."

ioclk_buf is an object of BUFPLL primitive that is used by me for generating high speed IO clock (half of the main clock).
Below is the ucf file of my design in which I want to display color bars on two screens simultaneously using HDMI ports on my Atlys board. Top level module of my design is also attached. What I think about this issue is that is due to incorrent floorplanning of bufpll (ioclk_buf).

###########################################
# Setting VCCAUX for different SP601 board
###########################################
VCCAUX = 3.3;
########################################
# Reset button and LEDs
########################################
NET "RSTBTN" LOC = "N4";
NET "LED<0>" LOC = "H12";
NET "LED<1>" LOC = "G13";
NET "LED<2>" LOC = "E16";
NET "LED<3>" LOC = "E18";
##############################################################################
# SYSCLK Input
##############################################################################
NET "SYS_CLK" LOC = "L15";
##############################################################################
# Mechanical Switches (SW)
##############################################################################
NET "SW<0>" LOC = "A10" |IOSTANDARD = LVCMOS33 ;
NET "SW<1>" LOC = "D14" |IOSTANDARD = LVCMOS33 ;
NET "SW<2>" LOC = "C14" |IOSTANDARD = LVCMOS33 ;
NET "SW<3>" LOC = "P15" |IOSTANDARD = LVCMOS33 ;
##############################################################################
# Debug Port # JA1
##############################################################################
NET "DEBUG[0]" LOC = "B12" |IOSTANDARD = LVCMOS33;
NET "DEBUG[1]" LOC = "B11" |IOSTANDARD = LVCMOS33;
##############################################################################
# DCM/PLL/BUFPLL positions
##############################################################################
#INST "PCLK_GEN_INST" LOC = "DCM_X0Y3";
#INST "PLL_OSERDES" LOC = "PLL_ADV_X0Y1";
#INST "ioclk_buf" LOC = "BUFPLL_X1Y0";
###########################################
# Timing Constraints
###########################################
NET "clk50m_bufg" TNM_NET = "TNM_CLK50M";
TIMESPEC "TS_CLK50M" = PERIOD "TNM_CLK50M" 50 MHz HIGH 50 % PRIORITY 0 ;
NET "pclk" TNM_NET = "TNM_PCLK";
TIMESPEC "TS_PCLK" = PERIOD "TNM_PCLK" 108 MHz HIGH 50 % PRIORITY 0 ;
NET "pclkx2" TNM_NET = "TNM_PCLKX2";
TIMESPEC "TS_PCLKX2" = PERIOD "TNM_PCLKX2" TS_PCLK * 2;
NET "pclkx10" TNM_NET = "TNM_PCLKX10";
TIMESPEC "TS_PCLKX10" = PERIOD "TNM_PCLKX10" TS_PCLK * 10;
#
# Multi-cycle paths
#
TIMEGRP "bramgrp" = RAMS(enc0/pixel2x/dataint<*>);
TIMEGRP "fddbgrp" = FFS(enc0/pixel2x/db<*>);
TIMEGRP "bramra" = FFS(enc0/pixel2x/ra<*>);
TIMEGRP "bramgrp" = RAMS(enc1/pixel2x/dataint<*>);
TIMEGRP "fddbgrp" = FFS(enc1/pixel2x/db<*>);
TIMEGRP "bramra" = FFS(enc1/pixel2x/ra<*>);
TIMESPEC "TS_ramdo" = FROM "bramgrp" TO "fddbgrp" TS_PCLK;
TIMESPEC "TS_ramra" = FROM "bramra" TO "fddbgrp" TS_PCLK;

############################
# TMDS pairs on the top
############################
NET "TMDS2(0)" LOC = "R3" |IOSTANDARD = TMDS_33 ; # Blue
NET "TMDSB2(0)" LOC = "T3" |IOSTANDARD = TMDS_33 ;
NET "TMDS2(1)" LOC = "T4" |IOSTANDARD = TMDS_33 ; # Red
NET "TMDSB2(1)" LOC = "V4" |IOSTANDARD = TMDS_33 ;
NET "TMDS2(2)" LOC = "N5" |IOSTANDARD = TMDS_33 ; # Green
NET "TMDSB2(2)" LOC = "P6" |IOSTANDARD = TMDS_33 ;
NET "TMDS2(3)" LOC = "T9" |IOSTANDARD = TMDS_33 ; # Clock
NET "TMDSB2(3)" LOC = "V9" |IOSTANDARD = TMDS_33 ;
NET "TMDS1(0)" LOC = "D8" |IOSTANDARD = TMDS_33 ; # Blue
NET "TMDSB1(0)" LOC = "C8" |IOSTANDARD = TMDS_33 ;
NET "TMDS1(1)" LOC = "C7" |IOSTANDARD = TMDS_33 ; # Red
NET "TMDSB1(1)" LOC = "A7" |IOSTANDARD = TMDS_33 ;
NET "TMDS1(2)" LOC = "B8" |IOSTANDARD = TMDS_33 ; # Green
NET "TMDSB1(2)" LOC = "A8" |IOSTANDARD = TMDS_33 ;
NET "TMDS1(3)" LOC = "B6" |IOSTANDARD = TMDS_33 ; # Clock
NET "TMDSB1(3)" LOC = "A6" |IOSTANDARD = TMDS_33 ;


Please help me in solving this issue. Thanks
            vtc_demo.v ‏21 KB

回帖（6）

石俊梅

2018-10-25 15:30:21
嗨，
我检查了设计。
BUFPLL的负载连接到与端口TMDS1
  • 和TMDS2
  • 相关联的OSERDES2。
    TMDS1端口锁定到IOBANK 0，TMDS2端口锁定到IOBANK 2。
    BUFPLL可以到达同一IO组中的IO负载。
    因此，请相应地更改约束，以便所有这些负载都锁定到同一个IO bank。
    谢谢，
    迪皮卡。
    谢谢，迪皮卡.----------------------------------------------
    ---------------------------------------------- Google之前的问题
    张贴。
    如果某人的帖子回答了您的问题，请将帖子标记为“接受为解决方案”。
    如果你看到一个特别好的和信息丰富的帖子，考虑给它Kudos（左边的明星）
    在原帖中查看解决方案

    以上来自于谷歌翻译


    以下为原文

    Hi,
     
    I have checked the design.
     
    The loads of BUFPLL are connected to OSERDES2 associated with ports TMDS1
  • and TMDS2
  • . The TMDS1 ports are locked to IOBANK 0 and  TMDS2 ports are locked to IOBANK 2.
     
    The BUFPLL can reach to IO loads which are in the same IO bank. So please change the constraints accordingly such that all these loads are locked to same IO bank.
     
    Thanks,
    Deepika.
    Thanks,
    Deepika.
    --------------------------------------------------------------------------------------------
    Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)View solution in original post
  • 和TMDS2
  • 相关联的OSERDES2。
    TMDS1端口锁定到IOBANK 0，TMDS2端口锁定到IOBANK 2。
    BUFPLL可以到达同一IO组中的IO负载。
    因此，请相应地更改约束，以便所有这些负载都锁定到同一个IO bank。
    谢谢，
    迪皮卡。
    谢谢，迪皮卡.----------------------------------------------
    ---------------------------------------------- Google之前的问题
    张贴。
    如果某人的帖子回答了您的问题，请将帖子标记为“接受为解决方案”。
    如果你看到一个特别好的和信息丰富的帖子，考虑给它Kudos（左边的明星）
    在原帖中查看解决方案

    以上来自于谷歌翻译


    以下为原文

    Hi,
     
    I have checked the design.
     
    The loads of BUFPLL are connected to OSERDES2 associated with ports TMDS1
  • and TMDS2
  • . The TMDS1 ports are locked to IOBANK 0 and  TMDS2 ports are locked to IOBANK 2.
     
    The BUFPLL can reach to IO loads which are in the same IO bank. So please change the constraints accordingly such that all these loads are locked to same IO bank.
     
    Thanks,
    Deepika.
    Thanks,
    Deepika.
    --------------------------------------------------------------------------------------------
    Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)View solution in original post
    • 举报

    石俊梅

    2018-10-25 15:41:37
    嗨，
    BUFPLL必须与其loadI / OLOGIC放在同一芯片侧。请检查BUFPLL的负载是如何锁定的，并确保它们与负载放在同一芯片侧。
    谢谢，
    迪皮卡。
    谢谢，迪皮卡.----------------------------------------------
    ---------------------------------------------- Google之前的问题
    张贴。
    如果某人的帖子回答了您的问题，请将帖子标记为“接受为解决方案”。
    如果你看到一个特别好的和信息丰富的帖子，考虑给它Kudos（左边的明星）

    以上来自于谷歌翻译


    以下为原文

    Hi,
     
    The BUFPLL must be placed in the same chip side as its load I/OLOGIC.Please check how are the loads of BUFPLL are locked and make sure that they are placed in same chip side as that of loads.
     
    Thanks,
    Deepika.
    Thanks,
    Deepika.
    --------------------------------------------------------------------------------------------
    Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
    举报

    张楠

    2018-10-25 15:46:42
    感谢您的回复@ vemulad.Pleasetell我如何检查BUFPLL的负载是否被锁定以及它们的放置位置。
    （我是FPGA设计的新手，对这些约束和布局规划知之甚少）。

    以上来自于谷歌翻译


    以下为原文

    Thanks for ur reply @vemulad. Please tell me that how can I check whether loads of BUFPLL are locked or not and where they are placed. (I am new toFPGA design and doesn't know much about these constraints and floorplanning).
    举报

    石俊梅

    2018-10-25 16:01:29
    嗨，
    您可以从ISE项目中打开后期综合PlanAhead（工具 - > PlanAhead  - > Post synthesis PlanAhead）。
    现在搜索错误中提到的BUFPLL实例。
    检查原理图中BUFPLL的IOLOGIC负载，并查看锁定与IOLOGIC负载元素对应的IO端口的位置。
    如果您可以共享ISE项目，我可以检查相同。
    谢谢，
    迪皮卡。
    谢谢，迪皮卡.----------------------------------------------
    ---------------------------------------------- Google之前的问题
    张贴。
    如果某人的帖子回答了您的问题，请将帖子标记为“接受为解决方案”。
    如果你看到一个特别好的和信息丰富的帖子，考虑给它Kudos（左边的明星）

    以上来自于谷歌翻译


    以下为原文

    Hi,
     
    You can open post synthesis PlanAhead (tools --> PlanAhead --> Post synthesis PlanAhead) from the ISE project.
     
    Now search for the BUFPLL instance mentioned in the error. Check the IOLOGIC loads of the BUFPLL in schematic and see to what locations did you lock the IO ports corresponding to the IOLOGIC load elements.
     
    If you can share the ISE project I can check the same.
     
    Thanks,
    Deepika.
    Thanks,
    Deepika.
    --------------------------------------------------------------------------------------------
    Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
    举报

    更多回帖

    6 0 0

    相关问答

    时序驱动
    发帖
    登录/注册
    电子发烧友APP
    |投诉反馈|电子发烧友网
    © 2021 bbs.elecfans.com
    湘ICP备2023018690号
    ×
    20
    完善资料，
    赚取积分