无法在XDC文件中设置maxdelay约束

我不确定我理解在输入路径上使用MAXDELAY的原理 - 这通常受ISE中OFFSET IN约束的约束。
同样，它应该在Vivado中用set_input_delay约束......
我不确定UG911指的是什么;
SDC set_max_delay可以限制路径上的延迟...也许是因为UCF中的MAXDELAY真的在网络上（而不是路径），工具说没有等效的......但是，你应该再次使用set_input_delay
这条路。
Avrum



以下为原文

I am not sure I understand your rationale for using a MAXDELAY on the input path - this is normally constrained with an OFFSET IN constraint in ISE.
 
Similarly, it should be constrained with a set_input_delay in Vivado...
 
I'm not sure what UG911 is referring to; the SDC set_max_delay can constrain the delay on a path... Perhaps because MAXDELAY in UCF was really on a net (rather than a path), the tool says there is no equivalent... But again, you should really use a set_input_delay for this path.
 
Avrum

对不起我的错误，我在OUTPUTpath上使用maxdelay约束而不在输入路径上使用。
例如，我在xilinx内存控制器（axi_emc）的输出上使用了这个约束。
Forall信号结果如下：
--------------------------------------------------
--------------------------------------------------
------约束|
检查|
最坏情况|
最佳案例|
时间安排|
时间安排|
|
松弛|
可实现的
错误|
得分了  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  - -
--------------------------------------------------
------- NET“axi_emc_0_Mem_DQ”|
MAXDELAY |
0.200ns |
0.000ns |
0 |
0
MAXDELAY = 0.2 ns |
|
|
|
|
--------------------------------------------------
--------------------------------------------------
------
WEN信号除外：
--------------------------------------------------
--------------------------------------------------
------ * NET“axi_emc_0_Mem_WEN_pin”|
MAXDELAY |
-0.283ns |
0.483ns |
1 |
283
MAXDELAY = 0.2 ns |
|
|
|
|
--------------------------------------------------
--------------------------------------------------
------
这不是一个真正的计时问题，但这为卡概念和示波器的物理信号分析提供了良好的指示。
杰罗姆



以下为原文

Sorry for my mistake, I use maxdelay constraint on OUTPUT path and not on input path. 
 
For example, I have used this constraint on the outputs of the xilinx memory controler (axi_emc). 
For all signals the result is the following :
----------------------------------------------------------------------------------------------------------
Constraint                               | Check          | Worst Case | Best Case  | Timing | Timing
                                               |                      |     Slack       | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
NET "axi_emc_0_Mem_DQ<0>"  | MAXDELAY |   0.200ns     | 0.000ns      | 0         | 0
MAXDELAY = 0.2  ns                   |                      |                     |                    |            |
----------------------------------------------------------------------------------------------------------
 
 
Excepted for the WEN signal :
----------------------------------------------------------------------------------------------------------
* NET "axi_emc_0_Mem_WEN_pin"  | MAXDELAY | -0.283ns| 0.483ns| 1| 283
MAXDELAY = 0.2 ns                          |                      |               |              |   |
---------------------------------------------------------------------------------------------------------- 
 
It's not a real timing problem but this gives a good indication for the card conception and for physical signal analysis with oscilloscope.
 
 
Jerome