- 调试环境:
我使用TMS320C5515 eZdsp USB Stick dsp单板,这个单板带有一个tlv320aic3204音频芯片;
目标:
我希望可以播放位速128kbps 音频采样大小 16位, 单声道,音频采用级别8kHz,音频格式为pcm的音频文件:
参考:
根据手册上的说明,要使用Mono方式,I2s需要使用DSP format.才有效,我将I2SSCTRL的FRMT置为1,这时就不能接收到音频信号,置为0则可以接收到音频信号。
问题:
请问tlv320aic3204 是否支持单音方式,能否提供参考配置,谢谢!
具体配置:
void aic3204_init_mono(void)
{
Uint16 regaddr;
SYS_EXBUSSEL = 0x6100; // Enable I2C bus
USBSTK5515_I2C_init( ); // Initialize I2C
/* Configure AIC3204 */
AIC3204_rset( 0, 0 ); // Select page 0
AIC3204_rset( 1, 1 ); // Reset codec
USBSTK5515_wait( 500 ); // Wait
AIC3204_rset( 0, 1 ); // Point to page 1
AIC3204_rset( 1, 8 ); // Disabled weak connection of AVDD with DVDD
AIC3204_rset( 2, 1 ); // Enable Analog Blocks, use LDO power (is LDO power being used? If it is, then this register needs to be set correclty to use LDO).
/* PLL and Clocks config and Power Up */
AIC3204_rset( 0, 0 ); // Select page 0
AIC3204_rset( 27, 0x4d ); // BCLK and WCLK is set as output from AIC3204(Master) 00: Audio Interface = dsp
AIC3204_rset( 28, 0x00 ); // Data ofset = 0
AIC3204_rset( 4, 3 ); // PLL setting: PLLCLK <- MCLK, CODEC_CLKIN <-PLL CLK
AIC3204_rset( 6, 8 ); // **PLL setting: J=8 (comment does not match)
AIC3204_rset( 7, 0x07 ); // PLL setting: HI_BYTE(D)
AIC3204_rset( 8, 0x80); // PLL setting: LO_BYTE(D)
AIC3204_rset( 30, 0x80 ); // For 32 bit clocks per frame in Master mode ONLY (make sure that BCLK >= [ (# bits per channel) * 2 ]
// BCLK=DAC_CLK/N =(12288000/8) = 1.536MHz = 32*fs
// For 8 KHz sampling
AIC3204_rset( 5, 0x91 ); // PLL setting: Power up PLL, P=1 and R=1
AIC3204_rset( 13, 0x01 ); // Hi_Byte(DOSR) for DOSR = 256 decimal or 0x01080 DAC oversamppling
AIC3204_rset( 14, 0x00 ); // Lo_Byte(DOSR) for DOSR = 256 decimal or 0x0100
AIC3204_rset( 20, 0x00 ); // AOSR for AOSR = 256 decimal or 0x0000 for decimation filters 1 to 6
AIC3204_rset( 11, 0x86 ); // Power up NDAC and set NDAC value to 3 (comments below differ from the values)
AIC3204_rset( 12, 0x88); // Power up MDAC and set MDAC value to 8 (comments below differ from the values)
AIC3204_rset( 18, 0x88 ); // Power up NADC and set NADC value to 8 (comments below differ from the values)
AIC3204_rset( 19, 0x86 ); // Power up MADC and set MADC value to 6 (comments below differ from the values)
AIC3204_rset( 60, 0x19 ); // Power up PRB_P25 for beep generator Selects the ADC (recording) signal processing block
AIC3204_rset( 61, 0x01 ); // ADC Singal Processing Block PRB_R1 ADC Signal Processing Block Control Register
AIC3204_rset( 48, 0xff ); // Power up MADC and set MADC value to 6 (comments below differ from the values)
AIC3204_rset( 49, 0xff ); // Power up PRB_P25 for beep generator
/* DAC ROUTING and Power Up */
AIC3204_rset( 0, 0x01 ); // Select page 1
AIC3204_rset( 12, 0x08 ); // LDAC AFIR routed to HPL
AIC3204_rset( 13, 0x08 ); // RDAC AFIR routed to HPR &&&&&&&
AIC3204_rset( 14, 0x00 ); // Right Channel DAC reconstruction filter's negative terminal is not routed to LOL
AIC3204_rset( 15, 0x00 ); // Right Channel DAC reconstruction filter output is not routed to LOR
AIC3204_rset( 0, 0x00 ); // Select page 0
AIC3204_rset( 64, 0x02 ); // Left vol=right vol
AIC3204_rset( 65, 0x00 ); // Left DAC gain to 0dB VOL; Right tracks Left
AIC3204_rset( 66, 0x81 ); // right mute
AIC3204_rset( 63, 0xd4 ); // Power up left,right data paths and set channel
AIC3204_rset( 0, 0x01 ); // Select page 1
AIC3204_rset( 20, 0x69 ); // Soft Step, De-pop, 6 time constants, 6k ohm.
AIC3204_rset( 16, 0x1d ); // Unmute HPL , 29dB gain
AIC3204_rset( 17, 0x3a ); // Unmute HPR , -6dB gain
AIC3204_rset( 9, 0x30 ); // Power up HPL,HPR
AIC3204_rset( 10, 0x33 ); // HP powered from LDOIN, CM voltage = 1.65V
AIC3204_rset( 0, 0x00 ); // Select page 0
USBSTK5515_wait( 500 ); // Wait
AIC3204_rset( 16, 15 ); // Unmute HPL set gain
AIC3204_rset( 17, 00 ); // Unmute HPR set gain
/* ADC ROUTING and Power Up */
AIC3204_rset( 0, 1 ); // Select page 1
//AIC3204_rset( 51, 0x40 ); // Mic Bias ON
AIC3204_rset( 52, 0x10 ); //IN2L is routed to Left MICPGA with 40K resistance
AIC3204_rset( 55, 0x00 ); //IN2R is not routed to Right MICPGA
AIC3204_rset( 54, 0x03 ); // CM is routed to Left MICPGA via CM2L with 40K resistance
AIC3204_rset( 57, 0x00 ); // CM is not routed to Right MICPGA
AIC3204_rset( 59, 0x80 ); // MIC_PGA_L unmute
AIC3204_rset( 60, 0x80 ); // MIC_PGA_R unmute
AIC3204_rset( 0, 0 ); // Select page 0
AIC3204_rset( 81, 0xa0 ); // Powerup Left and Right ADC
AIC3204_rset( 82, 0x04 ); // Unmute Left and Right ADC
// I2S settings
I2S0_SRGR = 0x0; //I2Sn Sample Rate Generator Register slave mode is invalide
I2S0_CR = 0x9011; // 16-bit word, slave, enable I2C Mono mode
//I2S2_CR = 0x9811;
//I2S0_CR = 0x8010;
// I2S0_CR Address: 0x2800 ((I2S BUS) I2Sn Serializer Control Register (I2SSCTRL)
// +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
// |15:14:13:12|11:10: 9: 8| 7: 6: 5: 4| 3: 2: 1: 0| <<== Bit Position
// +--+--+--+--+--+--+--+--+--+--+--+--+--+--:--:--+
// |rw:rw:rw:rw|rw:rw:rw:rw|rw:rw:rw:rw|rw:rw:rw:rw| <<== Read / Write Access
// +--+--+--+--+--+--+--+--+--+--+--+--+--+--:--:--+
// | 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| <<== Reset Values
// +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
// +--+--+--+--+--+--+--+--+--+--+--+--+--+--:--:--+
// | 1 0: 0: 1| 0: 0: 0: 0| 0: 0: 0: 1| 0: 0: 0: 1| <<== current Values
// +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
// | | | | | | | | | | | | | | | |
// | | | | | | | | | | | | | | | +-- [0] FRMT (0:I2S/left-justified format, 1:DSP format)
// | | | | | | | | | | | | | | +----- [1] MODE (0:Serializer is configured as a slave, 1:master)
// | | | | | | | | | | | | | +-------- [2] WDLNGTH (0:clk active, 1:clk disabled)
// | | | | | | | | | | | | +----------- [3] WDLNGTH Choose serializer word length 8 10 .. 32
// | | | | | | | | | | | |
// | | | | | | | | | | | +-------------- [4] WDLNGTH
// | | | | | | | | | | +----------------- [5] WDLNGTH
// | | | | | | | | | +-------------------- [6] SIGN_EXT (0:No sign extension, 1:Received data is sign extended. Transmit data is expected to be sign extended.For more information about sign extension)
// | | | | | | | | +----------------------- [7] PACK (0:Data packing mode disabled, 1:Data packing mode enabled)
// | | | | | | | |
// | | | | | | | +-------------------------- [8] DATADLY (0:1-bit data delay, 1:2-bit data delay)
// | | | | | | +----------------------------- [9] CLKPOL (0:Controls I2S clock polarity, 1:.....XXX $$$ )
// | | | | | +-------------------------------- [10] FSPOL (0:Inverts I2S frame-synchronization polarity, 1:....XXX $$$)
// | | | | +----------------------------------- [11] LOOPBACK (0:Normal operation, no loopback, 1:Digital Loopback mode enabled)
// | | | |
// | | | +-------------------------------------- [12] MONO (0:Stereo mode, 1:Mono mode. Valid only when bit 0, FRMT=1 (DSP Format))
// | | +----------------------------------------- [13] Reserved
// | +-------------------------------------------- [14] Reserved
// +----------------------------------------------- [15] ENABLE (0:I2S disabled, 1:I2S enabled)
I2S0_ICMR = 0x17; // Enable interrupts
//I2S0_ICMR = 0x3f;
// I2SINTMASK Address: 0x2814 ((I2S BUS) I2Sn Interrupt Mask Register (I2SINTMASK)
// +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
// |15:14:13:12|11:10: 9: 8| 7: 6: 5: 4| 3: 2: 1: 0| <<== Bit Position
// +--+--+--+--+--+--+--+--+--+--+--+--+--+--:--:--+
// |rw:rw:rw:rw|rw:rw:rw:rw|rw:rw:rw:rw|rw:rw:rw:rw| <<== Read / Write Access
// +--+--+--+--+--+--+--+--+--+--+--+--+--+--:--:--+
// | 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| <<== Reset Values
// +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
// +--+--+--+--+--+--+--+--+--+--+--+--+--+--:--:--+
// | 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 1| 0: 1: 0: 0| <<== current Values
// +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
// | | | | | | | | | | | | | | | |
// | | | | | | | | | | | | | | | +-- [0] OUERR (0:Disable overrun/underrun error interrupt, 1:Enable overrun/underrun error interrupt.)
// | | | | | | | | | | | | | | +----- [1] FERR (0:Disable frame-synchronization error interrupt, 1:Enable frame-synchronization error interrupt.)
// | | | | | | | | | | | | | +-------- [2] RCVMON (0:Disable mono RX data interrupt, 1:Enable mono RX data interrupt.)
// | | | | | | | | | | | | +----------- [3] RCVST (0:Disable stereo RX data interrupt, 1:Enable stereo RX data interrupt)
// | | | | | | | |
// | | | | | | | | | | | |
// | | | | | | | | | | | +-------------- [4] XMITMON (0:Disable mono TX data interrupt, 1:Enable mono TX data interrupt)
// | | | | | | | | | | +----------------- [5] XMITST (0:Disable stereo TX data interrupt, 1:Enable stereo TX data interrupt)
// | | | | | | | | | +-------------------- [6] Reserved
// | | | | | | | | +----------------------- [7] Reserved
// | | | | | | | |
// | | | | | | | +-------------------------- [8] Reserved
// | | | | | | +----------------------------- [9] Reserved
// | | | | | +-------------------------------- [10] Reserved
// | | | | +----------------------------------- [11] Reserved
// | | | |
// | | | +-------------------------------------- [12] Reserved
// | | +----------------------------------------- [13] Reserved
// | +-------------------------------------------- [14] Reserved
// +----------------------------------------------- [15] Reserved
}
0
|
3个回答
|
|
|