[问答]

Quartus提示Error (10500): XXX.vhd(266) near text "ctrview"; expecting "entity", or.......怎么解决？

5288 FPGA

问答对人有帮助，内容完整，我也想知道答案 0 刚学不太懂，完整代码如下： -------------------------------------------------------------------4位二进制并行进位加法器的源程序ADDER4B.VHD如下： LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENtiTY ADDER4B IS PORT(ci:IN STD_LOGIC; a:IN STD_LOGIC_VECTOR(3 DOWNTO 0); b:IN STD_LOGIC_VECTOR(3 DOWNTO 0); s:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); co:OUT STD_LOGIC ); END ADDER4B; ARCHITECTURE behave OF ADDER4B IS SIGNAL SINT:STD_LOGIC_VECTOR(4 DOWNTO 0); --类似于在芯片 --部定义的一个数据 SIGNAL aa,bb:STD_LOGIC_VECTOR(4 DOWNTO 0); BEGIN aa<='0' & a; --拓展位数，使其成为最高位 bb<='0' & b; SINT<=aa+bb+ci; --相加 s<=SINT(3 DOWNTO 0); co<=SINT(4); --最高位为输出进位位 END behave; -------------------------------------------------------------------顶层模块：8位二进制并行进位加法器的部分程序ADDER4B.VHD如下： LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY ADDER8B IS PORT(ci:IN STD_LOGIC; a:IN STD_LOGIC_VECTOR(7 DOWNTO 0); b:IN STD_LOGIC_VECTOR(7 DOWNTO 0); s:OUT STD_LOGIC_VECTOR(7 DOWNTO 0); co:OUT STD_LOGIC ); END ADDER8B; ARCHITECTURE a OF ADDER8B IS COMPONENT ADDER4B --引用4位二进制并行进位加法器 PORT(ci:IN STD_LOGIC; a:IN STD_LOGIC_VECTOR(3 DOWNTO 0); b:IN STD_LOGIC_VECTOR(3 DOWNTO 0); s:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); co:OUT STD_LOGIC ); END COMPONENT; SIGNAL CARRY_OUT:STD_LOGIC; BEGIN U1:ADDER4B PORT MAP(ci=>ci,a=>a(3 DOWNTO 0),b=>b(3 DOWNTO 0),s=>s(3 DOWNTO 0),co=>CARRY_OUT); U2:ADDER4B PORT MAP(ci=>CARRY_OUT,a=>a(7 DOWNTO 4),b=>b(7 DOWNTO 4),s=>s(7 DOWNTO 4),co=>co); END a; -------------------------------------------------------------------------4位二进制并行进位减法器的源程序suber.VHD如下： LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY suber IS PORT(a:IN STD_LOGIC_VECTOR(3 DOWNTO 0); b:IN STD_LOGIC_VECTOR(3 DOWNTO 0); ci:IN STD_LOGIC; s:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); co:OUT STD_LOGIC ); END suber; ARCHITECTURE behave OF suber IS COMPONENT adder IS --引用加法器的模块 PORT(a:IN STD_LOGIC; b:IN STD_LOGIC; ci:IN STD_LOGIC; s:OUT STD_LOGIC; co:OUT STD_LOGIC ); END COMPONENT; SIGNAL btem:STD_LOGIC_VECTOR(3 DOWNTO 0); --减数寄存 SIGNAL ctem:STD_LOGIC_VECTOR(4 DOWNTO 0); --进位寄存 SIGNAL stem:STD_LOGIC_VECTOR(3 DOWNTO 0); --结果寄存 BEGIN btem(3 DOWNTO 0)<=NOT b (3 DOWNTO 0); --先把减数求反 ctem(0)<=NOT ci; --输出进位也求反，从而对减数求补码 g1:FOR i IN 0 TO 3 GENERATE --连用4位全加器 add:adder PORT MAP (a(i),btem(i),ctem(i),stem(i),ctem(i+1)); END GENERATE; s(3 downto 0)<=stem(3 downto 0); --结果输出 co<=NOT ctem(4); --求反输出进位 END behave; ----------------------------------------------------------------------------------乘法器的源程序： LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY mul IS PORT ( a,b : IN STD_LOGIC_VECTOR(3 DOWNTO 0); y : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) );END mul; ARCHITECTURE arch OF mul IS BEGIN y(7 DOWNTO 0) <= a(3 DOWNTO 0)b(3 DOWNTO 0); END arch; -----------------------------------------------------------------------------------除法器的源程序： LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY diver IS PORT(a:IN STD_LOGIC_VECTOR(7 DOWNTO 0); b:IN STD_LOGIC_VECTOR(3 DOWNTO 0); clk:IN STD_LOGIC; str:IN STD_LOGIC; s:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); y:OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ); END ; ARCHITECTURE behave OF diver IS COMPONENT suber IS --引用减法器 PORT(a:IN STD_LOGIC_VECTOR(3 DOWNTO 0); b:IN STD_LOGIC_VECTOR(3 DOWNTO 0); ci:IN STD_LOGIC; s:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); co:OUT STD_LOGIC ); END COMPONENT; TYPE state_type IS (start,one,two,three,eror); --状态定义 SIGNAL state:state_type; SIGNAL ain:STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL bin:STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL atem:STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL btem:STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL stem:STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL citem:STD_LOGIC; SIGNAL cotem:std_logic; BEGIN p2:PROCESS(clk) VARIABLE n: INTEGER range 0 to 3; --移位次数计数值 BEGIN IF clk'EVENT AND clk='1' THEN CASE state IS WHEN start=> --开始状态 IF str='1' THEN state<=one; atem(3 DOWNTO 0)<=a(7 DOWNTO 4); --把高4位放到减法器被减数端 btem(3 DOWNTO 0)<=b(3 DOWNTO 0); --把除数放到减法器减数端 ain(7 DOWNTO 0)<=a(7 DOWNTO 0); --寄存被除数 bin(3 DOWNTO 0)<=b(3 DOWNTO 0); --寄存除数 END IF; WHEN one=> --第一次移位 IF cotem='0' THEN state<=eror; ELSE ain(3 downto 1)<=ain(2 downto 0); --被除数做移位 ain(0)<=not cotem; --在最低位接受该位商值 atem(3 downto 0)<=ain(6 downto 3); --除数寄存器高4位输到减法器，作为被减数 state<=two; END IF; WHEN two=> --第二次移位 IF n=2 THEN state<=three; n:=0; ELSE state<=two; n:=n+1; END IF; IF cotem='0' THEN atem(3 DOWNTO 1)<=stem(2 DOWNTO 0); ELSE atem(3 DOWNTO 1)<=atem(2 DOWNTO 0); END IF; ain(3 DOWNTO 1)<=ain(2 DOWNTO 0); ain(0)<=NOT cotem; atem(0)<=ain(3); WHEN three=> --第三次移位 s(3 DOWNTO 1)<=ain(2 DOWNTO 0); s(0)<=NOT cotem; IF cotem='0' THEN y(3 DOWNTO 0)<=atem(3 DOWNTO 0); ELSE y(3 DOWNTO 0)<=atem(3 DOWNTO 0); END IF; atem(3 DOWNTO 0)<="0"; btem(3 DOWNTO 0)<="0"; state<=start; WHEN eror=> --溢出状态 state<=start; --回到开始状态 atem(3 DOWNTO 0)<="0"; btem(3 DOWNTO 0)<="0"; END CASE; END IF; END PROCESS p2; citem<='0'; U1:suber PORT MAP (atem,btem,citem,stem,cotem); END behave; ----------------------------------------------------------------------------------------数字按键译码电路VHDL语言描述： LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY numdecoder IS PORT(reset:IN STD_LOGIC; inclk:IN STD_LOGIC; innum:STD_LOGIC_VECTOR(9 DOWNTO 0); outnum:BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0); outflag:OUT STD_LOGIC); END; ARCHITECTURE behave OF numdecoder IS BEGIN PROCESS(inclk,reset) BEGIN IF reset='1'THEN outnum<="0000"; ELSIF inclk'EVENT AND inclk='1'THEN CASE innum IS WHEN"0000000001"=>outnum<="0000";outflag<='1'; --按下第一个键表示输入0 WHEN"0000000010"=>outnum<="0001";outflag<='1'; --以下类似 WHEN"0000000100"=>outnum<="0010";outflag<='1'; WHEN"0000001000"=>outnum<="0011";outflag<='1'; WHEN"0000010000"=>outnum<="0100";outflag<='1'; WHEN"0000100000"=>outnum<="0101";outflag<='1'; WHEN"0001000000"=>outnum<="0110";outflag<='1'; WHEN"0010000000"=>outnum<="0111";outflag<='1'; WHEN"0100000000"=>outnum<="1000";outflag<='1'; WHEN"1000000000"=>outnum<="1001";outflag<='1'; WHEN OTHERS=>outnum<=outnum;outflag<='0'; --不按键时保持 END CASE; END IF; END PROCESS; END behave; ------------------------------------------------------------------------------7段译码器的VHDL语言描述： LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY vdecode IS PORT(indata:IN STD_LOGIC_VECTOR(3 DOWNTO 0); outdata:OUT STD_LOGIC_VECTOR(0 TO 6) ); END; ARCHITECTURE behave OF vdecode IS BEGIN WITH indata SELECT outdata<="1111110"WHEN"0000", --0的显示，以下类似 "0110000"WHEN"0001", "1101101"WHEN"0010", "1111001"WHEN"0011", "0110011"WHEN"0100", "1011011"WHEN"0101", "1011111"WHEN"0110", "1110000"WHEN"0111", "1111111"WHEN"1000", "0000000"WHEN OTHERS; END behave; ----------------------------------------------------------------------------8位二进制数转换成个位、十位、百位的进程： ctrview:PROCESS(c,clk) BEGIN IF c='1'THEN view1<="0000"; view2<="0000"; view3<="0000"; viewstep<=takenum; ELSIF clk'EVENT AND clk='1'THEN CASE viewstep IS WHEN takenum=> ktemp<=keep; viewstep<=hundred=>; IF ktemp>="11001000"THEN --如果ktemp大于200 view1<="0010";ktemp<=ktemp-"11001000"; --百位为2，ktemp－200 ELSIF ktemp>="01100100"THEN --如果ktemp大于100 view1<="0001";ktemp<=ktemp-"01100100"; --百位为1，ktemp－100 ELSE view1<="0000"; --百位为0 END IF; viewstep<=ten; WHEN ten=> --产生十位数字 IF ktemp>="01011010"THEN view2<="1001";ktemp<=ktemp-"01011010"; ELSIF ktemp>="01010000"THEN view2<="1000";ktemp<=ktemp-"01010000"; ELSIF ktemp>="01000110"THEN view2<="0111";ktemp<=ktemp-"01000110"; ELSIF ktemp>="00111100"THEN view2<="0110";ktemp<=ktemp-"00111100"; ELSIF ktemp>="00110010"THEN view2<="0101";ktemp<=ktemp-"00110010"; ELSIF ktemp>="00101000"THEN view2<="0100";ktemp<=ktemp-"00101000"; ELSIF ktemp>="00011110"THEN view2<="0011";ktemp<=ktemp-"00011110"; ELSIF ktemp>="00010100"THEN view2<="0010";ktemp<=ktemp-"00010100"; ELSIF ktemp>="00001010"THEN view2<="0001";ktemp<=ktemp-"00001010"; ELSE view2<="0000"; END IF; viewstep<=one WHEN one=> --产生个位数字 view3<=ktemp(3 DOWNTO 0); viewstep<=takenum; WHEN OTHERS=>NULL; END CASE; END IF; END PROCESS ctrview; ---------------------------------------------------------------计算器的VHDL语言： LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY keshe IS PORT (inclk: IN STD_LOGIC; num: IN STD_LOGIC_VECTOR(9 DOWNTO 0); plus: IN STD_LOGIC; --加法按键 subt: IN STD_LOGIC; --减法按键 mult: IN STD_LOGIC; --乘法按键 mdiv: IN STD_LOGIC; --除法按键 equal: IN STD_LOGIC; --等号键 c: IN STD_LOGIC; --清零键 onum1,onum2,onum3: OUT STD_LOGIC_VECTOR(0 TO 6) ); --3个7段译码显示管 END keshe; ARCHITECTURE behave OF keshe IS TYPE state IS (takenum,hundred,ten,one); SIGNAL viewstep: state; SIGNAL ktemp: STD_LOGIC_VECTOR(7 DOWNTO 0); --分为显示的暂存器 SIGNAL flag: STD_LOGIC; --是否是第一次输入数字的标志符 SIGNAL f1: STD_LOGIC; --是否开始输入第二个数字的标志 SIGNAL acc: STD_LOGIC_VECTOR(7 DOWNTO 0); --存放第一个数字的累加器 SIGNAL reg: STD_LOGIC_VECTOR(7 DOWNTO 0); --存放第二个以及以后数字的寄存器 SIGNAL keep: STD_LOGIC_VECTOR(7 DOWNTO 0); --存放显示数字的寄存器 SIGNAL ans: STD_LOGIC_VECTOR(7 DOWNTO 0); --存放各步计算结果的寄存器 SIGNAL dans: STD_LOGIC_VECTOR(3 DOWNTO 0); --存放除法结果的寄存器 SIGNAL numbuff: STD_LOGIC_VECTOR(3 DOWNTO 0); --输入数字缓冲 SIGNAL vf: STD_LOGIC; --表示是否最后结果 SIGNAL strdiv: STD_LOGIC; --除法计算开始的信号 SIGNAL numclk: STD_LOGIC; --将数字从缓存放入累加器或寄存器 SIGNAL clear: STD_LOGIC; --清除累加器中的信号 SIGNAL inplus: STD_LOGIC; --同步加信号 SIGNAL insubt: STD_LOGIC; --同步减信号 SIGNAL inmult: STD_LOGIC; --同步乘信号 SIGNAL inmdiv: STD_LOGIC; --同步除信号 SIGNAL inequal: STD_LOGIC; --同步等于信号 SIGNAL view1,view2,view3: STD_LOGIC_VECTOR(3 DOWNTO 0); --分位的显示 --------------------------------------------------------——寄存器 SIGNAL cou: STD_LOGIC_VECTOR(1 DOWNTO 0); --用力记忆是第几次 --计算的信号 SIGNAL clk_gg: STD_LOGIC_VECTOR(11 DOWNTO 0); --用于产生分频时钟的信号 SIGNAL clk: STD_LOGIC; --分频后的时钟信号 COMPONENT numdecoder IS --引用数字按键的译码电路 PORT ( reset: IN STD_LOGIC; inclk: IN STD_LOGIC; innum: IN STD_LOGIC_VECTOR(9 DOWNTO 0); outnum: BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0); outflag: OUT STD_LOGIC ); END COMPONENT; COMPONENT vdecode IS --引用7段译码器 PORT(indata:IN STD_LOGIC_VECTOR(3 DOWNTO 0); outdata:OUT STD_LOGIC_VECTOR(0 TO 6)); END COMPONENT; COMPONENT diver IS --引用除法器 PORT( a: IN STD_LOGIC_VECTOR(7 DOWNTO 0); b: IN STD_LOGIC_VECTOR(3 DOWNTO 0); clk: IN STD_LOGIC; str: IN STD_LOGIC; s: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); y: OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ); END COMPONENT; BEGIN inum1: numdecoder port map(c,clk,num,numbuff,numclk); clock: PROCESS(inclk,c) --进程clock用于产生分频的时钟，使得12位向 --量clk_gg不断加1，然后输出12位中的某一位 BEGIN IF c='1' THEN clk_gg(11 DOWNTO 0)<="0"; ELSIF inclk'EVENT AND inclk='1' then clk_gg(11 DOWNTO 0)<=clk_gg(11 DOWNTO 0)+1; END IF; END PROCESS clock; clk<=clk_gg(11); pacecal: PROCESS(c,clk) BEGIN IF c='1' then inplus<='0';insubt<='0';inmult<='0';inmdiv<='0'; ELSIF clk'EVENT AND clk='1' then IF plus='1' then inplus<='1'; insubt<='0';inmult<='0';inmdiv<='0'; ELSIF subt='1' then inplus<='0';insubt<='1';inmult<='0';inmdiv<='0'; ELSIF mult='1' then inplus<='0';insubt<='0';inmult<='1';inmdiv<='0'; ELSIF mdiv='1' then inplus<='0';insubt<='0';inmult<='0';inmdiv<='1'; END IF; END IF; END PROCESS pacecal; ctrflag: PROCESS(c,clk) --用于产生flag信号 BEGIN IF c='1' then flag<='0'; ELSIF clk'EVENT AND clk='1' then IF inplus='1' OR insubt='1' OR inmult='1' OR inmdiv='1' THEN flag<='1'; ELSE flag<='0'; END IF; END IF; END PROCESS ctrflag; ctrfirstnum: PROCESS(c,numclk) --用于输入第一个运算数 BEGIN IF c='1' then acc<="00000000"; ELSIF numclk'EVENT AND numclk='0' then IF flag='0' then acc<=acc"1010"+numbuff; END IF; END IF; END PROCESS ctrfirstnum; ctrsecondnum:PROCESS(c,numclk) --用于输入第二个以后的运算数字 BEGIN IF c='1'OR clear='1'THEN reg<="00000000";f1<='0'; ELSIF numclk'event AND numclk='0'THEN IF flag='1'THEN f1<='1'; reg<=reg"1010"+numbuff; END IF; END IF; END PROCESS ctrsecondnum; ctrclear: PROCESS(c,clk) --用于产生clear信号 BEGIN IF c='1' then clear<='0'; ELSIF clk'EVENT AND clk='1' then IF plus='1' OR subt='1' then clear<='1'; ELSE clear<='0'; END IF; END IF; END PROCESS ctrclear; ctrinequal:PROCESS(c,clk) --用于产生inqual信号 BEGIN IF c='1' then inequal<='0'; ELSIF clk'EVENT AND clk='1' then IF plus='1' OR subt='1' OR mult='1' OR mdiv='1' OR equal='1' then inequal<='1'; ELSE inequal<='0'; END IF; END IF; END PROCESS ctrinequal; ctrcou: process (c,inequal) --用于产生cou信号 BEGIN IF c='1' then cou<="00"; ELSIF inequal'EVENT and inequal='1'then IF cou="10" then cou<=cou; ELSE cou<=cou+1; END IF; END IF; END PROCESS ctrcou; ctrcal: PROCESS (c,inequal) --用于实现运算 BEGIN IF c='1' then ans<="00000000"; strdiv<='0'; ELSIF inequal'EVENT and inequal='1' then IF flag='1' then IF inplus='1' then IF cou="10" then ans<=ans+reg; END IF; ELSIF insubt='1'THEN IF cou="10"THEN ans<=ans-reg; ELSE ans<=acc-reg; END IF; ELSIF inmult='1' then IF acc<="00001111" AND reg<="00001111" then --将乘数和被乘数限制在4位二进制数范围内 ans<=acc(3 DOWNTO 0) reg(3 downto 0); ELSE ans<="00000000"; END IF; ELSIF inmdiv='1'THEN strdiv<='1'; END IF; else strdiv<='0'; END IF; END IF; END PROCESS ctrcal; d1:diver PORT MAP (acc,reg(3 DOWNTO 0),clk,strdiv,dans); --将除法结果放在dans中 ctrvf: PROCESS(c,equal) --用来产生vf信号 BEGIN IF c='1' then vf<='0'; ELSIF equal'EVENT AND equal='1' then vf<='1'; END IF; END PROCESS ctrvf; ctrkeep: process(c,clk) --用于控制keep寄存器 BEGIN IF c='1' then --keep寄存器清零 keep<="00000000"; ELSIF clk'EVENT AND clk='0' then IF flag='0' then --输入第二个数以前keep中存放acc中的数 keep<=acc; ELSIF flag='1' AND f1='1' AND vf='0' then --输入第二个数以前keep中存放reg中的数 keep<=reg; ELSIF flag='1' AND f1='0'AND vf='0'AND cou="10" then --keep中存放ans中的内容 keep<=ans; ELSIF flag='1'and vf='1'then --最终的计算结果 IF inmdiv='0'THEN keep<=ans; ELSE keep(3 DOWNTO 0)<=dans; END IF; END IF; END IF; END PROCESS ctrkeep; ctrview:PROCESS(c,clk) BEGIN IF c='1'THEN view1<="0000"; view2<="0000"; view3<="0000"; viewstep<=takenum; ELSIF clk'EVENT AND clk='1'THEN CASE viewstep IS WHEN takenum=> ktemp<=keep; viewstep<=hundred; WHEN hundred=> IF ktemp>="11001000"THEN view1<="0010";ktemp<=ktemp-"11001000"; ELSIF ktemp>="01100100"THEN view1<="0001";ktemp<=ktemp-"01100100"; ELSE view1<="0000"; END IF; viewstep<=ten; WHEN ten=> IF ktemp>="01011010"THEN view2<="1001";ktemp<=ktemp-"01011010"; ELSIF ktemp>="01010000"THEN view2<="1000";ktemp<=ktemp-"01010000"; ELSIF ktemp>="01000110"THEN view2<="0111";ktemp<=ktemp-"01000110"; ELSIF ktemp>="00111100"THEN view2<="0110";ktemp<=ktemp-"00111100"; ELSIF ktemp>="00110010"THEN view2<="0101";ktemp<=ktemp-"00110010"; ELSIF ktemp>="00101000"THEN view2<="0100";ktemp<=ktemp-"00101000"; ELSIF ktemp>="00011110"THEN view2<="0011";ktemp<=ktemp-"00011110"; ELSIF ktemp>="00010100"THEN view2<="0010";ktemp<=ktemp-"00010100"; ELSIF ktemp>="00001010"THEN view2<="0001";ktemp<=ktemp-"00001010"; ELSE view2<="0000"; END IF; viewstep<=one; WHEN one=> view3<=ktemp(3 DOWNTO 0); viewstep<=takenum; WHEN OTHERS=>NULL; END CASE; END IF; END PROCESS ctrview; v1:vdecode PORT MAP (view1,onum1); --7段译码显示百位 v2:vdecode PORT MAP (view2,onum2); --7段译码显示十位 v3:vdecode PORT MAP (view3,onum3); --7段译码显示个位 END behave; 0 已退回4积分
2021-7-3 00:39:10　　评论淘帖0 邀请回答您可以邀请以下用户，快速回答问题 × 刘英该类别下有 31 个回答。邀请回答 chenbingjy 该类别下有 27 个回答。邀请回答 yoonssica 该类别下有 22 个回答。邀请回答 houxiaoxiao 该类别下有 17 个回答。邀请回答小萃米该类别下有 16 个回答。邀请回答小工兵该类别下有 16 个回答。邀请回答 Elecfans管家该类别下有 15 个回答。邀请回答薄迪该类别下有 14 个回答。邀请回答我爱妖妖该类别下有 14 个回答。邀请回答言尽于此33 该类别下有 14 个回答。邀请回答 hxing 该类别下有 13 个回答。邀请回答那些年儿ing 该类别下有 13 个回答。邀请回答平漂流该类别下有 13 个回答。邀请回答 xiekaboy 该类别下有 12 个回答。邀请回答 1653344032.827400 该类别下有 12 个回答。邀请回答小麦地该类别下有 12 个回答。邀请回答科比如我该类别下有 12 个回答。邀请回答倪love 该类别下有 12 个回答。邀请回答 2013crazy 该类别下有 11 个回答。邀请回答英雄孤寂该类别下有 11 个回答。邀请回答举报 lyp82nxb 相关推荐 • quartus错误10500解决办法 15710 • 急求程序提示错误 5704 • FPGA程序问题 3922 • 麻烦问一下这个程序出现的错误怎么修改？ 6933 • 新人求教关于VHDL移位的问题 2445 • DECODER5-32有错，新手，希望得到帮助 3137 • 求救大神，学渣用VHDL编了个与非门，出现简单错误怎么解决 3285 • 在Quartus中编译时出现Error: WYSIWYG primitive "pll" is not 错误如... 7543 • 求教大神们这个程序错在哪里了 3585 • Error: Flash Download failed - "Cortex-M4" 11593 1个回答

答案对人有帮助，有参考价值 0 VHDL掌握不太熟练，只能做如下建议： //------expecting "entity" 感觉像是语法问题，缺少实体，建议分段排查。 //------分段排查如果代码多，就全部注释，然后分段释放代码；如果代码少，分段注释。这样便于以一种“无脑”的方式圈定错误范围。 //------其他我这边看到的是一大段代码，通常情况下建议分成多个文件来写，每个文件完成不同的功能。

2021-7-3 15:19:54 评论举报卿小小_9e6