28335ADC DMA采样正弦信号失真问题如何解决

我用TMS320F28335对一个正弦信号进行采样，频率约为1kHz，正弦信号中的直流偏置为1.65v，通过CCS6.0中的Graph工具看采集的数据波形时，发现连续多个采样信号之间的值相等，整个波形呈现锯齿状，如下图所示(两个图中的数据相同，使用bar模式看的更清楚些)，ADC和DMA模块的初始化代码如下：
void pwmset()//EPWM初始化代码
[
EPwm1Regs.TBPRD=50;//4us;
EPwm1Regs.TBCTR=0;
EPwm1Regs.TBPHS.all=0;
EPwm1Regs.TBCTL.bit.FREE_SOFT=1;
EPwm1Regs.TBCTL.bit.CLKDIV=1;//sys/12
EPwm1Regs.TBCTL.bit.HSPCLKDIV=3;
EPwm1Regs.TBCTL.bit.PRDLD=0;
EPwm1Regs.TBCTL.bit.PHSEN=0;
EPwm1Regs.TBCTL.bit.CTRMODE=0;
EPwm1Regs.ETSEL.bit.SOCAEN=1;
EPwm1Regs.ETSEL.bit.SOCASEL=2;
EPwm1Regs.ETSEL.bit.SOCBEN=0;
EPwm1Regs.ETPS.bit.SOCAPRD=1;
]
void adcset()//ADC初始化代码
[
InitAdc();
AdcRegs.ADCTRL1.bit.ACQ_PS=1;//预定标系数=1
AdcRegs.ADCTRL1.bit.CONT_RUN=0;//非连续运行
AdcRegs.ADCTRL1.bit.CPS=1;//ADC模块时钟预分频
AdcRegs.ADCTRL1.bit.SEQ_CASC=1;//SEQ级联模式
AdcRegs.ADCTRL2.bit.EPWM_SOCB_SEQ=0;//
AdcRegs.ADCTRL2.bit.RST_SEQ1=1;
AdcRegs.ADCTRL2.bit.SOC_SEQ1=0;
AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1=1;
AdcRegs.ADCTRL2.bit.INT_MOD_SEQ1=0;
AdcRegs.ADCTRL2.bit.EPWM_SOCA_SEQ1=1;
AdcRegs.ADCTRL2.bit.EXT_SOC_SEQ1=0;
AdcRegs.ADCTRL3.bit.SMODE_SEL=0;
AdcRegs.ADCTRL3.bit.ADCCLKPS=3;//12.5Mh;
AdcRegs.ADCCHSELSEQ1.bit.CONV00=0;
AdcRegs.ADCCHSELSEQ1.bit.CONV01=1;
AdcRegs.ADCCHSELSEQ1.bit.CONV02=2;
AdcRegs.ADCCHSELSEQ1.bit.CONV03=3;
AdcRegs.ADCCHSELSEQ2.bit.CONV04=4;
AdcRegs.ADCCHSELSEQ2.bit.CONV05=5;
AdcRegs.ADCMAXCONV.bit.MAX_CONV2=0x5;
// AdcRegs.ADCMAXCONV.bit.MAX_CONV1=0x0;
]

void dmaset()//DMA初始化代码
[
DMAInitialize();
DMADest=&DMABuf1[0];
DMASource= &AdcMirror.ADCRESULT0;
DMACH1AddrConfig(DMADest,DMASource);
DMACH1BurstConfig(6,1,512);//设置每次Burst的字节数、源地址增量、目标地址增量
DMACH1TransferConfig(511,0,0);//设置每次传送包含多少个Burst、传送完毕发中断，源地址增量、目标地址增量
DMACH1WrapConfig(0,0,0,1);//no use wrap;
EALLOW;
// Set up MODE Register:
DmaRegs.CH1.MODE.bit.PERINTSEL = DMA_SEQ1INT; // Passed DMA channel as peripheral interrupt source
DmaRegs.CH1.MODE.bit.PERINTE = PERINT_ENABLE; // Peripheral interrupt enable
DmaRegs.CH1.MODE.bit.ONESHOT = ONESHOT_DISABLE; // Oneshot disable, tansfer won't stop between bursts
DmaRegs.CH1.MODE.bit.CONTINUOUS = CONT_ENABLE; // Continous enable, channel won't be disabled at the end of transfer
DmaRegs.CH1.MODE.bit.SYNCE = SYNC_DISABLE; // Peripheral sync enable/disable
DmaRegs.CH1.MODE.bit.SYNCSEL = SYNC_SRC; // Sync effects source or destination
DmaRegs.CH1.MODE.bit.OVRINTE = OVRFLOW_DISABLE; // Enable/disable the overflow interrupt
DmaRegs.CH1.MODE.bit.DATASIZE = SIXTEEN_BIT; // 16-bit/32-bit data size transfers
DmaRegs.CH1.MODE.bit.CHINTMODE = CHINT_END; // Generate interrupt to CPU at beginning/end of transfer
DmaRegs.CH1.MODE.bit.CHINTE = CHINT_ENABLE; // Channel Interrupt to CPU enable(PIE)
// Clear any spurious flags:
DmaRegs.CH1.CONTROL.bit.PERINTCLR = 1; // Clear any spurious interrupt flags
DmaRegs.CH1.CONTROL.bit.SYNCCLR = 1; // Clear any spurious sync flags
DmaRegs.CH1.CONTROL.bit.ERRCLR = 1; // Clear any spurious sync error flags
// Initialize PIE vector for CPU interrupt:
// Enable DMA CH1 interrupt in PIE
EDIS;
]