AIC3254的寄存器配置不通该怎么办？

你好，
我现在正在测试AIC3254的环出：模拟信号进行A/D转换生成数字信号后，经过了一个均衡器，再进行D/A转化为模拟信号经过HeadPhone输出。调了几天了，都不通，不知道哪里有问题。
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我的硬件是将AIC3254与DM8168的McASP[0]想连接。3254的MCLK由外部晶振提供，频率为24.576KHz。设置采样率为44.1KHz。计算时钟见下图。

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我在PPS里的编程如下：

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我将生成的代码通过PPS写入评估板，评估板能正常工作。然后我把生成的寄存器数组（修改电源，时钟，接口，通道后）通过自己的程序写入3254芯片，却没有输出。
下面是我修改后的寄存器代码(自己修改的寄存器后都有注释/////////////)：
static const t_i2c_reg i2c_aic3254[] = [/*[[[*/
[ 0,0x00],
// # reg[ 0][ 1] = 0x01 ; Initialize the device through software reset
[ 1,0x01],
[254,0x0A],
[ 0,0x01],
// # reg[ 1][ 1] = 0x08 ; Power up AVDD LDO; Disable weak AVDD to DVDD connection; Enable Master Analog Power Control, AVDD LDO Powered; Disable weak AVDD to DVDD connection
[ 1,0x08],
// # reg[ 1][ 2] = 0x00 ; Enable Master Analog Power Control
[ 2,0xF0],////////////////
// # reg[ 1][ 71] = 0x32 ; Set the input power-up time to 3.1ms
[ 71,0x32],
// # reg[ 1][123] = 0x01 ; Set REF charging time to 40ms (automatic)
[123,0x01],
[255,0x00],
[255,0x01],
[ 0,0x00],
// # reg[ 0][ 60] = 0x00 ; DAC prog Mode: miniDSP_A and miniDSP_D NOT powered up together, miniDSP_A used for signal processing
[ 60,0x00],
// # reg[ 0][ 61] = 0x00 ; Use miniDSP_A for signal processing
[ 61,0x00],
// # reg[ 0][ 17] = 0x08 ; 8x Interpolation
[ 17,0x08],
// # reg[ 0][ 23] = 0x04 ; 4x Decimation
[ 23,0x04],
//
[ 15,0x03],
//
[ 16,0x88],
//
[ 21,0x03],
//
[ 22,0x88],
[ 0,0x08],
// # reg[ 8][ 1] = 0x04 ; adaptive mode for ADC
[ 1,0x04],
[ 0,0x2C],
// # reg[ 44][ 1] = 0x04 ; adaptive mode for DAC
[ 1,0x04],
[ 0,0x00],
// # reg[ 0][ 5] = 0x91 ; P=1, R=1, J=8
[ 5,0xA1],///////// # PLL is powered up;P=2;R=1
// # reg[ 0][ 6] = 0x08 ; P=1, R=1, J=8
[ 6,0x07],///////// J=7
// # reg[ 0][ 7] = 0x00 ; D=0000 (MSB)
[ 7,0x0D],///////// D=3500(MSB)
// # reg[ 0][ 8] = 0x00 ; D=0000 (LSB)
[ 8,0xAC],///////// D=3500(LSB)
// # reg[ 0][ 4] = 0x03 ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on
[ 4,0x43],///////////
// # reg[ 0][ 12] = 0x88 ; MDAC = 8, divider powered on
[ 12,0x82],/////////M=2
// # reg[ 0][ 13] = 0x00 ; DOSR = 128 (MSB)
[ 13,0x00],
// # reg[ 0][ 14] = 0x80 ; DOSR = 128 (LSB)
[ 14,0x80],
// # reg[ 0][ 18] = 0x02 ; NADC = 2, divider powered off
[ 18,0x08],/////////N=8
// # reg[ 0][ 19] = 0x88 ; MADC = 8, divider powered on
[ 19,0x82],/////////M=2
// # reg[ 0][ 20] = 0x80 ; AOSR = 128
[ 20,0x80],
// # reg[ 0][ 11] = 0x82 ; NDAC = 2, divider powered on
[ 11,0x88],/////////N=8

///////////////////////////////////// Audio Interface Settings
[0x1b,0x0c],//////// # I2S;16bit;BCLK output;WCLK output
[0x1c,0x00],//////// # Data Offset = 0BCLK
[0x1d,0x03],////////
[0x1e,0x82],////////
[0x20,0x00],////////
[0x21,0x18],////////

[ 0,0x01],
// # reg[ 1][ 51] = 0x40 ; Mic Bias enabled, Source = Avdd, 1.25V
[ 51,0x40],
// # reg[ 1][ 52] = 0x40 ; Route IN2L to LEFT_P with 10K input impedance; Route CM1L to LEFT_M with 10K input impedance; Route IN2R to RIGHT_P with 10K input impedance; Route IN1L to LEFT_P with 10K input impedance
[ 52,0x55],///////// # Route IN1_L IN2_L IN3_L IN1_R to Input LEFT_P
// # reg[ 1][ 54] = 0x40 ; Route CM1L to LEFT_M with 10K input impedance
[ 54,0x40],
// # reg[ 1][ 55] = 0x40 ; Route IN1R to RIGHT_P with 10K input impedance
[ 55,0x55],//////// # Route IN1_R IN2_R IN2_R IN2_L to Output RIGHT_P
// # reg[ 1][ 57] = 0x40 ; Route CM1R to RIGHT_M with 10K input impedance
[ 57,0x40],
// # reg[ 1][ 59] = 0x00 ; Enable MicPGA_L Gain Control, 0dB
[ 59,0x00],
// # reg[ 1][ 60] = 0x00 ; Enable MicPGA_R Gain Control, 0dB
[ 60,0x00],
[ 0,0x00],
// # reg[ 0][ 81] = 0xc0 ; Power up LADC/RADC
[ 81,0xC0],
// # reg[ 0][ 82] = 0x00 ; Unmute LADC/RADC
[ 82,0x00],
[0x53,0x14],///////// # ADC_L Gain 10dB
[0x54,0x14],///////// # ADC_L Gain 10dB
[ 0,0x01],
// # reg[ 1][ 20] = 0x25 ; De-pop: 5 time constants, 6k resistance
[ 20,0x25],
// # reg[ 1][ 12] = 0x08 ; Route LDAC to HPL
[ 12,0x0a],/////////
// # reg[ 1][ 13] = 0x08 ; Route RDAC to HPR
[ 13,0x0a],/////////
// # reg[ 1][ 14] = 0x08 ; Route LDAC to LOL
[ 14,0x08],
// # reg[ 1][ 15] = 0x08 ; Route LDAC to LOR
[ 15,0x08],
[ 0,0x00],
// # reg[ 0][ 63] = 0xd4 ; Power up LDAC/RDAC w/ soft stepping
[ 63,0xD4],
[ 0,0x01],
// # reg[ 1][ 16] = 0x00 ; Unmute HPL driver, 0dB Gain
[ 16,0x00],
// # reg[ 1][ 17] = 0x00 ; Unmute HPR driver, 0dB Gain
[ 17,0x00],
// # reg[ 1][ 18] = 0x00 ; Unmute LOL driver, 0dB Gain
[ 18,0x00],
// # reg[ 1][ 19] = 0x00 ; Unmute LOR driver, 0dB Gain
[ 19,0x00],
// # reg[ 1][ 9] = 0x3c ; Power up HPL/HPR and LOL/LOR drivers
[ 9,0x3C],
[ 0,0x00],
// # reg[ 0][ 64] = 0x00 ; Unmute LDAC/RDAC
[ 64,0x00],
// # reg[0][82] = 0
[ 82,0x00],
// # reg[0][83] = 0
[ 83,0x00],
// # reg[0][86] = 32
[ 86,0x20],
// # reg[0][87] = 254
[ 87,0xFE],
// # reg[0][88] = 0
[ 88,0x00],
// # reg[0][89] = 104
[ 89,0x68],
// # reg[0][90] = 168
[ 90,0xA8],
// # reg[0][91] = 6
[ 91,0x06],
// # reg[0][92] = 0
[ 92,0x00],
// # reg[0][84] = 0
[ 84,0x00],
// # reg[0][94] = 32
[ 94,0x20],
// # reg[0][95] = 254
[ 95,0xFE],
// # reg[0][96] = 0
[ 96,0x00],
// # reg[0][97] = 104
[ 97,0x68],
// # reg[0][98] = 168
[ 98,0xA8],
// # reg[0][99] = 6
[ 99,0x06],
// # reg[0][100] = 0
[100,0x00],
[0, 0xFF],
];/*]]]*/

static const t_i2c_reg miniDSP_A_reg_values[] = [
   。。。。
];

static const t_i2c_reg miniDSP_A_reg_values[] = [
   。。。。
];