[问答]

Spartan 6在240MHz部分时序失败该怎么办？

问答对人有帮助，内容完整，我也想知道答案 0 我有一个Spartan 6，主要是60MHz的时钟，但有一个时钟频率为240MHz（以及60MHz）。那部分与其他一切非常分开。今天我尝试在我的项目中添加一个新模块。它是一个SPI从控制器 - 本质上它需要一个SPI命令，并写入或读取几个寄存器。很简单。它的实例化只有6个端口 - 4条SPI线（MISO，MOSI，SCK和nCS），复位和时钟（60MHz）。 SPI线直接连接到芯片上的引脚。添加这个使我开始在240MHz部分失败时序。同样，新部分和旧部分之间的唯一连接是60MHz时钟和复位线。任何人都可以建议我试着再次开始计时吗？或者我可以在ISE中使用哪些选项？我可以共享（私下）代码 - 但我怀疑这对于某人来说是很费时的。谢谢！以上来自于谷歌翻译以下为原文 I have a Spartan 6 that is mostly clocked at 60MHz, but has one section that is clocked at 240MHz (along with 60MHz). That section is very separate from everything else. Today I tried to add in a new module to my project. It is a SPI slave controller - essentially it takes a SPI command and writes to or reads from a couple of registers. Very simple. The instantiation of it has only 6 ports - the 4 SPI lines (MISO, MOSI, SCK, and nCS), reset, and clock (60MHz). The SPI lines are directly connected to pins on the chip. Adding this in makes me start to fail timing in the 240MHz section. Again, the only connection between the new section and the old section is the 60MHz clock and the reset line. Can anybody suggest what I might look at to try to start meeting timing again? Or perhaps are there options within ISE that I can play with? I can share (privately) the code - but I suspect that that would be time consuming for somebody to look at. Thank you! 0
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答案对人有帮助，有参考价值 0 我首先来看看警告信息会有一堆，通常我会确定我已修复它们或者至少知道我无法修复它们以及它们为什么会发生。 sartan 6是一个很好的部分，但它确实受到限制时钟功能的影响。它很容易把时钟放在错误的一边等。而240 MHz正在推动Spartan 6部分，只是芯片周围240 MHz模块的运动可能会导致您的性能下降。芯片有多满？确保你使用所有快速有用的位，就像内置注册的rams，不是异步的，IOB寄存器，然后看看调整报告，布局和你的约束，毫无魔力就是增加工具的投入量，但除非这是绝对的最后一次构建，否则这只是一个间隙答案。以上来自于谷歌翻译以下为原文 Id start by wading through the warning messages there will be a bunch, and as a rule I'd make certain I have either fixed them or at least know I can't fix them and why they are happening. The sartan 6 is a great part, but it does suffer with restricted clocking capabilities. its easy to end up putting clock in on the wrong side etc. and 240 MHz is pushing the Spartan 6 part, just the movment of the 240 MHz blocks around the chip could have killed your performance. How full is the chip ? make certain your using all the fast helpfull bits you can, like the built in registered rams, not asyncronous, the IOB registers, then its down to looking at the timming reports, the layout and your constraints, the none magic is to up the amount of effort the tools put in, but unless this is the absolute last build , that is but a stop gap answer.

2019-7-30 06:51:52 评论举报张磊