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我有一个SPARTAN3E板,用它来从相机获取数据。
然而,经过多次尝试,我观察到摄像机的VSYNC正确进入FPGA(用LA检查),但是如果使用内部时钟锁存并发送到FPGA的另一个引脚,则相同的VSYNC(没有任何修改)似乎有 很多故障。 这是令人惊讶的,因为模拟显示没有问题并且VSYNC正确到来。 它也是一种低频信号。 有什么方法可以检查SPARTAN3E是否正常,以及FPGA本身是否存在问题? 请让我知道如何继续。 以上来自于谷歌翻译 以下为原文 I have a SPARTAN3E board and am using it for getting data from a camera. However after several attempts , I observe that the VSYNC from the camera comes into the FPGA correctly (checked with LA) , but this same VSYNC (without any modification) if latch with an internal clock and sent to another pin of the FPGA seems to have many glitches. This is surprising since the simulation shows no problem and the VSYNC is coming correctly. It is also a low frequency signal . Is there any way I can check to see if the SPARTAN3E is okay, and if there are some problems on the FPGA itself? Please let me know how to proceed. |
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2个回答
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K,
它是Xilinx主板(或我们的合作伙伴之一)吗? 如果是这样,可能会有自我测试模式。 否则,您可以创建自检以检查其是否有效。 FPGA器件坚固耐用,使用寿命长(正常使用时> 25年)。 ESD可能会破坏或损坏设备,以及其他绝对最大额定值已大大超过的情况。 几乎工作,但有一些故障,可能是电缆或连接问题(坏焊点等)。 你有另一块有效的电路板吗? Austin Lesea主要工程师Xilinx San Jose 以上来自于谷歌翻译 以下为原文 k, Is it a Xilinx board (or one of our partners)? If so, there may be a self-test pattern for it. Otherwise, it is up to you to create a self test to check that it works. FPGA devices are robust, and long lived (> 25 years under normal use). ESD may destroy or damage the device, as well as other cases where the absolute maximum ratings have been greatly exceeded. Amost working, but with some glitches, is likely a cable or connection problem (bad solder joint, and such). Do you have another board that works? Austin Lesea Principal Engineer Xilinx San Jose |
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不幸的是,这是唯一的董事会。
这是一个Papilio板。 检查了所有连接。 一个有趣的事情我注意到输入。 我在UCF文件中定义了VSYNC和HREF输入 NET CAM_HREF LOC =“P10”| IOSTANDARD = LVTTL | DRIVE = 8 | SLEW =快; NET CAM_VSYNC LOC =“P11”| IOSTANDARD = LVTTL | DRIVE = 8 | SLEW =快; 但在设计报告中我发现HREF没有IO寄存器且没有IOB延迟,但是VSYNC有一个IO寄存器,延迟为3.我在VSYNC中遇到了大部分问题我想(看看笔记本电脑上的图像) 为什么两个相似的信号实现方式不同? 如何使CAM_VSYNC与CAM_HREF类似? 以上来自于谷歌翻译 以下为原文 This is the only board unfortunately. It is a Papilio board. Have checked all connections. One funny thing I notice about inputs. I have defined in UCF file both the VSYNC and HREF inputs as NET CAM_HREF LOC = "P10" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; NET CAM_VSYNC LOC = "P11" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; But in the design report I find HREF has no IO register and no IOB delay but VSYNC has an IO register and a delay of 3. I mostly am experiencing problems in VSYNC I guess (looking at the image on the laptop) Why is that two similar signals are implemented differently ? How do I make the CAM_VSYNC similar to CAM_HREF ? |
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