[问答]

ISE 12.4升级后使用Spartan 6的设计中没有映射

问答对人有帮助，内容完整，我也想知道答案 0 你好，我在ISE 12.4中使用Spartan 6进行了设计。我设法生成了编程文件，并且工作正常。经过一些修改后，我已迁移到ISE 14.7，现在设计没有映射。我在映射期间出现“Place：543”错误（以及其他错误）。我使用我的源文件创建了一个新项目。我还使用MIG再次创建了DDR2控制器，但我没有成功。我是否必须更改工作区的某些设置？有人遇到过同样的问题吗？最好的祝福。以上来自于谷歌翻译以下为原文 Hello, I have a design in ISE 12.4 with Spartan 6. I managed to generate the programming file and it worked fine. After some modifications I have migrated to ISE 14.7, and now the design doesn't map. I get "Place:543" error (among others) during Mapping. I have created a new project using my source files. I have also created again the DDR2 controller using MIG, but I don't manage to succeed. DO I have to change some setting of the workspace? Anyone has had the same kind of problem? Best regards. 0
2019-7-26 07:07:46　　评论淘帖0 邀请回答您可以邀请以下用户，快速回答问题 × asd008 该类别下有 32 个回答。邀请回答 aaaa321 该类别下有 27 个回答。邀请回答 doublelove 该类别下有 26 个回答。邀请回答 vynywrwr 该类别下有 21 个回答。邀请回答 hgjhgd 该类别下有 19 个回答。邀请回答 bwerwer 该类别下有 18 个回答。邀请回答 hanyan533 该类别下有 18 个回答。邀请回答 Jaionm 该类别下有 18 个回答。邀请回答 handsomelchcpp 该类别下有 17 个回答。邀请回答 wang2222222 该类别下有 17 个回答。邀请回答 ningee 该类别下有 16 个回答。邀请回答 binro 该类别下有 16 个回答。邀请回答 wznnzw 该类别下有 15 个回答。邀请回答 myf888 该类别下有 15 个回答。邀请回答 yhxc 该类别下有 14 个回答。邀请回答 armortech 该类别下有 14 个回答。邀请回答 60user25 该类别下有 14 个回答。邀请回答 zcy615 该类别下有 14 个回答。邀请回答 wanglinhua2627 该类别下有 14 个回答。邀请回答 guotong1984 该类别下有 14 个回答。邀请回答举报蓝孝增相关推荐 • 是否可以将ISE升级到版本12.4并保留相同的许可证？ 2318 • 是否可以从Xilinx ISE 10.1升级到Xilinx ISE 11.1而无需付费？ 2308 • 版本12.4安装是否可以使用可自定义的安装功能？ 1488 • ISE12.4中出现“map.exe”错误 2619 • ISE webpack 11.2没有virtex 6或spartan 6系列 1712 • RK3399升级为ubuntu20.04后无法连接wifi怎么解决？ 723 • 将Non-OS SDK从1.3.0升级到1.4.0后，AT CWLAP命令将无法再找到我的AP，为什么？ 368 • 请问如果用u盘给CH559升级，有没有相关的例程呢？ 760 • 想通过串口去给ch32v203升级程序，请问硬件上有什么要求吗 784 • 为什么使用ISE模板为spartan 6使用块发挥作用时会发生警告？ 2022 2个回答

答案对人有帮助，有参考价值 0 你能把完整的错误信息复制到这个帖子吗？ --Krishna 以上来自于谷歌翻译以下为原文 can you copy the complete error message to this thread? --Krishna

2019-7-26 07:21:49 评论举报刘丰标

答案对人有帮助，有参考价值 0 你好，关于BLOCKRAM的一部分如下：我对LUT 118（2.3）和FF 95（0.8）有相同的错误 .........................错误：地点：543 - 由于设备的复杂性，此设计不适合此设备中可用的切片数量设计和/或约束。未按类型放置的实例：BLOCKRAM 100（94.3）请评估以下内容： - 如果存在用户定义的约束或区域组：请查看下面的“用户定义的约束”部分，以确定可能影响其拟合的约束条件设计。评估它们是否可以移动，移除或调整大小以允许拟合。验证它们是否与时钟区域限制重叠或冲突。有关时钟区域使用的更多详细信息，请参阅MAP日志文件（* map）中的时钟区域报告。 - 如果放置LUT有困难：尝试使用MAP LUT组合选项（映射lc区域\|自动\|关闭）。 - 如果放置FF有困难：评估设计中控制集的数量和配置。以下实例是未能放置的最后一组实例：0。BLOCKRAM UCORE1 / UUPSAMPLER / Mram_BUS_0008_GND_160_o_wide_mux_33_OUT1 1. BLOCKRAM UCORE_0 / UUPSAMPLER / Mram_BUS_0008_GND_160_o_wide_mux_33_OUT1 2. BLOCKRAM UREM / instruction_unit / icache / memories [0] .way_0_tag_ram / Mram_mem 3. Placer RPM“Ppc”（大小：3）BLOCKRAM UCORE_1 / USPI / gSPI_NORM.UOUTPUT / UFIFO / Mram_SM_RAM 4. Placer RPM“Ppc”（大小：3）BLOCKRAM UCORE_1 / UDV / UHP_TS_CODING / UINTERLEAVER / UBRAM0 / Mram_mem 5. Placer RPM“ Ppc“（大小：3）BLOCKRAM UCORE_1 / UDV / UINNER_INTERLEAVER / USYMBOL_INTERLEAVER / Mram_MEM1 ...相同的100个错误.... 这些实例可能受以下约束影响（下面的行ID与上面的实例对应）：时钟区域限制2. CLOCKREGION_X0Y5，CLOCKREGION_X1Y5 93. CLOCKREGION_X0Y5，CLOCKREGION_X1Y5 94. CLOCKREGION_X0Y5，CLOCKREGION_X1Y5 95. CLOCKREGION_X0Y5，CLOCKREGION_X1Y5 96. CLOCKREGION_X0Y5，CLOCKREGION_X1Y5 97 .CLOCKREGION_X0Y5，CLOCKREGION_X1Y5 98. CLOCKREGION_X0Y5，CLOCKREGION_X1Y5 99. CLOCKREGION_X0Y5，CLOCKREGION_X1Y5 以上来自于谷歌翻译以下为原文 Hello, A part regarding BLOCKRAM is the following one: I have the same errors for LUT 118 (2.3) and FF 95 (0.8) ......................... ERROR:Place:543 - This design does not fit into the number of slices available in this device due to the complexity of the design and/or constraints. Unplaced instances by type: BLOCKRAM 100 (94.3) Please evaluate the following: - If there are user-defined constraints or area groups: Please look at the "User-defined constraints" section below to determine what constraints might be impacting the fitting of this design. Evaluate if they can be moved, removed or resized to allow for fitting. Verify that they do not overlap or conflict with clock region restrictions. *See the clock region reports in the MAP log file (map) for more details on clock region usage. - If there is difficulty in placing LUTs: Try using the MAP LUT Combining Option (map lc area\|auto\|off). - If there is difficulty in placing FFs: Evaluate the number and configuration of the control sets in your design. The following instances are the last set of instances that failed to place: 0. BLOCKRAM UCORE1/UUPSAMPLER/Mram_BUS_0008_GND_160_o_wide_mux_33_OUT1 1. BLOCKRAM UCORE_0/UUPSAMPLER/Mram_BUS_0008_GND_160_o_wide_mux_33_OUT1 2. BLOCKRAM UREM/instruction_unit/icache/memories[0].way_0_tag_ram/Mram_mem 3. Placer RPM "Ppc" (size: 3) BLOCKRAM UCORE_1/USPI/gSPI_NORM.UOUTPUT/UFIFO/Mram_SM_RAM 4. Placer RPM "Ppc" (size: 3) BLOCKRAM UCORE_1/UDV/UHP_TS_CODING/UINTERLEAVER/UBRAM0/Mram_mem 5. Placer RPM "Ppc" (size: 3) BLOCKRAM UCORE_1/UDV/UINNER_INTERLEAVER/USYMBOL_INTERLEAVER/Mram_MEM1 ... THE SAME UNTIL 100 ERRORs .... These instances could be impacted by the following constraints (the line IDs below correspond with the instances above): Clock Region restrictions 2. CLOCKREGION_X0Y5, CLOCKREGION_X1Y5 93. CLOCKREGION_X0Y5, CLOCKREGION_X1Y5 94. CLOCKREGION_X0Y5, CLOCKREGION_X1Y5 95. CLOCKREGION_X0Y5, CLOCKREGION_X1Y5 96. CLOCKREGION_X0Y5, CLOCKREGION_X1Y5 97. CLOCKREGION_X0Y5, CLOCKREGION_X1Y5 98. CLOCKREGION_X0Y5, CLOCKREGION_X1Y5 99. CLOCKREGION_X0Y5, CLOCKREGION_X1Y5**

2019-7-26 07:39:04 评论举报辛太励