FPGA同步从FIFO进入失速状态正常吗？

我在自己的流媒体应用（我们收集的高速串行数据流，将其转换为并行，运输起来USB）。我们有一个FPGA做的串口- >；并行转换，做自己的内部fifoing，喂养FX2接口作为一个主人的奴隶。（8位总线，同步--我想--，40mhz IFC时钟由FPGA提供脉冲时，SLWR有数据的饲料，等）。
当我用cyconsole，我的设备出现，我在终点的报道，并且能够读取512个字节时，我做了一个大。
我可以写用CyAPI函数重复一次做xferdata() 512字节的应用。我的数据流是不够快，但是，FX2的FIFO满时，我被迫降数据。（我管理大约4Mb/s）
所以，我切换到重叠IO（beginxfer、WaitForXfer、FinishXfer）再次用512字节，我可以管理8Mb／s，但我还是被迫降数据（我们产生约10Mb/s）。
所以我开始用大转移（32KB，例如），此时FX2 / FPGA操作一段时间，然后会摔倒，进入失速状态。我不知道这是否正常。
我怀疑这是当FX2的FIFO为空（这只会发生在当我把足够的数据的系统，我可以排在FPGA FX2的FIFO和4KB FIFO），我没有权利在这一点上做的事情。
TL；DR：什么原因造成了在autoin Slave FIFO模式的端点批量进入失速状态？我本来期望的端点以NAK数据之前，就做好准备，不失速。（充分披露，我没有检查USB总线，但当我拿到城市统计后管锁表示停顿）
我可以发我的奴隶的储蓄。我的C和Win32的C简单流源代码日当我到办公室。



     以下为原文
  I'm working on my own streaming application (we're collecting high speed serial bitstream, converting it to parallel, and shipping it up USB).  We have an FPGA doing the serial->parallel conversion,  doing its own internal FIFOing, and feeding the FX2 slave interface as a master. (8 bit bus, synchronous--i think--, 40Mhz IFC clock sourced by the FPGA, SLWR pulsed when there's data to feed, etc).
    When I use the cyconsole, my device shows up, reports my in end points, and is able to read 512 bytes when I do a bulk in.
    I can write an application using CYApi to repeatedly do XferData() 512 bytes at a time.   My data stream is fast enough, however, that the FX2 fifo gets full and I'm forced to drop data. (I manage about 4MB/s)
    So, I switched to overlapped IO (BeginXfer, WaitForXfer, FinishXfer) again with 512 bytes, and I can manage about 8MB/s, but I'm still being forced to drop data (we generate about 10MB/s).
    So I started using large transfers (32KB, for example), at this point FX2/FPGA operate for a short time, and then would fall over and enter a stall state.  I don't know if this is normal or not.
    I suspect this is when the FX2 FIFO becomes empty (which only happens when I'm transferring  enough data out of the system that I can drain the FX2 FIFO and the 4KB fifo on the FPGA) and I'm not doing something right at that point.  
    TL;DR:   what can cause a bulk in endpoint in AUTOIN Slave FIFO mode to enter stall state?   I would have expected the endpont to NAK until data became ready, not stall.  (full disclosure, I haven't examined the USB bus, but when I get the URB stat after the pipe locks up it says stalled)
    I can post the entirity of my slave.c and my win32 C simple streaming source code on monday when I get into the office.